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Re: [Qemu-devel] [PATCH 4/5] openrisc: Initial SMP support
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 4/5] openrisc: Initial SMP support |
Date: |
Thu, 12 Oct 2017 14:28:03 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 08/22/2017 10:57 PM, Stafford Horne wrote:
> Wire in ompic and add basic support for SMP. The OpenRISC is special in
> that interrupts for devices are routed to each core's PIC. This is
> achieved using the qemu_irq_split utility, but this currently limits
> OpenRISC to 2 cores.
>
> This models the reference architecture described in the OpenRISC spec
> 1.2 proposal.
>
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> The changes to the intialization of the sim include:
>
> CPU Reset
> o Reset each cpu to the bootstrap PC rather than only a single cpu as
> done before.
> o During Kernel loading the bootstrap PC is saved in a static global.
>
> Network Initialization
> o Connect the interrupt to each CPU
> o Use more simple sysbus_mmio_map() rather than memory_region_add_subregion()
>
> Sim Initialization
> o Initialize the pic and tick timer per cpu
> o Wire in the OMPIC if SMP is enabled
> o Wire the serial irq to each CPU using qemu_irq_split()
>
> Signed-off-by: Stafford Horne <address@hidden>
> ---
> hw/openrisc/openrisc_sim.c | 84
> +++++++++++++++++++++++++++++++++-------------
> 1 file changed, 61 insertions(+), 23 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
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