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[Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDF
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit |
Date: |
Fri, 6 Oct 2017 16:59:45 +0100 |
When we added support for the new SHCSR bits in v8M in commit
437d59c17e9 the code to support writing to the new HARDFAULTPENDED
bit was accidentally only added for non-secure writes; the
secure banked version of the bit should also be writable.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index bd1d5d3..22d5e6e 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1230,6 +1230,7 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
(value & (1 << 18)) != 0;
+ s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) !=
0;
/* SecureFault not banked, but RAZ/WI to NS */
s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;
--
2.7.4
- [Qemu-devel] [PULL 16/20] nvic: Implement Security Attribution Unit registers, (continued)
- [Qemu-devel] [PULL 16/20] nvic: Implement Security Attribution Unit registers, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 09/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 12/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 10/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 08/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 03/20] hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit,
Peter Maydell <=
- [Qemu-devel] [PULL 02/20] hw/sd: fix out-of-bounds check for multi block reads, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state", Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 17/20] target/arm: Implement security attribute lookups for memory accesses, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 01/20] arm: Fix SMC reporting to EL2 when QEMU provides PSCI, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 05/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 06/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/10/06
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2017/10/06