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Re: [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers |
Date: |
Thu, 5 Oct 2017 14:33:23 -0400 |
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Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the register interface for the SAU: SAU_CTRL,
> SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the
> actual behaviour is implemented here; registers just
> read back as written.
>
> When the CPU definition for Cortex-M33 is eventually
> added, its initfn will set cpu->sau_sregion, in the same
> way that we currently set cpu->pmsav7_dregion for the
> M3 and M4.
>
> Number of SAU regions is typically a configurable
> CPU parameter, but this patch doesn't provide a
> QEMU CPU property for it. We can easily add one when
> we have a board that requires it.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/cpu.h | 10 +++++
> hw/intc/armv7m_nvic.c | 116
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.c | 27 ++++++++++++
> target/arm/machine.c | 14 ++++++
> 4 files changed, 167 insertions(+)
Reviewed-by: Richard Henderson <address@hidden>
r~
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