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[Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg an
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar |
Date: |
Wed, 4 Oct 2017 14:43:20 -0400 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0cd58710b3..ee1e364fb5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6941,10 +6941,42 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
+ break;
+ case 14: /* VQRDMLAH scalar */
+ case 15: /* VQRDMLSH scalar */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1_SIMD)) {
+ return 1;
+ }
+ if (u && ((rd | rn) & 1)) {
+ return 1;
+ }
+ tmp2 = neon_get_scalar(size, rm);
+ for (pass = 0; pass < (u ? 4 : 2); pass++) {
+ void (*fn)(TCGv_i32, TCGv_env, TCGv_i32,
+ TCGv_i32, TCGv_i32);
-
+ tmp = neon_load_reg(rn, pass);
+ tmp3 = neon_load_reg(rd, pass);
+ if (op == 14) {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlah_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlah_s32;
+ }
+ } else {
+ if (size == 1) {
+ fn = gen_helper_neon_qrdmlsh_s16;
+ } else {
+ fn = gen_helper_neon_qrdmlsh_s32;
+ }
+ }
+ fn(tmp, cpu_env, tmp, tmp2, tmp3);
+ tcg_temp_free_i32(tmp3);
+ neon_store_reg(rd, pass, tmp);
+ }
+ tcg_temp_free_i32(tmp2);
break;
- default: /* 14 and 15 are RESERVED */
+ default:
return 1;
}
}
--
2.13.6
- [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 01/12] HACK: use objdump disas, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 03/12] target/arm: Decode aa64 armv8.1 scalar three same extra, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 04/12] target/arm: Decode aa64 armv8.1 three same extra, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 06/12] target/arm: Decode aa32 armv8.1 three same, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar,
Richard Henderson <=
- [Qemu-devel] [PATCH v1 09/12] target/arm: Decode aa64 armv8.3 fcadd, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 10/12] target/arm: Decode aa64 armv8.3 fcmla, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 08/12] target/arm: Add ARM_FEATURE_V8_FCMA, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 11/12] target/arm: Decode aa32 armv8.3 3-same, Richard Henderson, 2017/10/04
- [Qemu-devel] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index, Richard Henderson, 2017/10/04
- Re: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04
- Re: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04
- Re: [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns, no-reply, 2017/10/04