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Re: [Qemu-devel] [PATCH v3 1/6] tcg: Add types and operations for host v
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 1/6] tcg: Add types and operations for host vectors |
Date: |
Wed, 27 Sep 2017 09:18:50 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 09/26/2017 12:28 PM, Alex Bennée wrote:
>> * TCGv_ptr : a host pointer type
>> + * TCGv_vec : a host vector type; the exact size is not exposed
>> + to the CPU front-end code.
>
> Isn't this a guest vector type (which is pointed to by a host pointer)?
No, it's a host vector, which we have created in response to expanding a guest
vector operation.
> A one line comment wouldn't go amiss here. This looks like we are
> allocating a new temp of the same type as an existing temp?
>
>> +TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match)
Yes.
>> +All of the vector ops have a final constant argument that specifies the
>> +length of the vector operation LEN as 64 << LEN bits.
>
> That doesn't scan well. So would a 4 lane operation be encoded as 64 <<
> 4? Is this because we are using the bottom bits for something?
64 << 0 = 64
64 << 1 = 128
64 << 2 = 256.
I've fixed up the wording a bit.
>> + Copy C across the entire vector.
>> + At present the only supported values for C are 0 and -1.
>
> I guess this is why the size in unimportant? This is for clearing or
> setting the whole of the vector? What does len mean in this case?
Yes. Len still means the length of the whole vector.
Elsewhere there's a comment about maybe using dupi{8,16,32,64}_vec instead.
However I wanted to put that off until we do some more conversions and see
exactly what's going to be needed.
>> +* and_vec v0, v1, v2, len
>> +* or_vec v0, v1, v2, len
>> +* xor_vec v0, v1, v2, len
>> +* andc_vec v0, v1, v2, len
>> +* orc_vec v0, v1, v2, len
>> +* not_vec v0, v1, len
>> +
>> + Similarly, logical operations.
>
> Similarly, logical operations with and without compliment?
Sure.
r~
- [Qemu-devel] [PATCH v3 0/6] TCG vectorization and example conversion, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 3/6] target/arm: Align vector registers, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 1/6] tcg: Add types and operations for host vectors, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 4/6] target/arm: Use vector infrastructure for aa64 add/sub/logic, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 2/6] tcg: Add vector expanders, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 5/6] tcg/i386: Add vector operations, Richard Henderson, 2017/09/15
- [Qemu-devel] [PATCH v3 6/6] tcg/aarch64: Add vector operations, Richard Henderson, 2017/09/15
- Re: [Qemu-devel] [PATCH v3 0/6] TCG vectorization and example conversion, Richard Henderson, 2017/09/15
- Re: [Qemu-devel] [PATCH v3 0/6] TCG vectorization and example conversion, no-reply, 2017/09/26