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[Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRC
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear |
Date: |
Thu, 21 Sep 2017 17:41:22 +0100 |
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
preempt execution. The simple way to achieve this is to clear the
enable bit for it, since the enable bit isn't guest visible.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 0c1d591..35225c8 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -937,11 +937,16 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
(R_V7M_AIRCR_SYSRESETREQS_MASK |
R_V7M_AIRCR_BFHFNMINS_MASK |
R_V7M_AIRCR_PRIS_MASK);
- /* BFHFNMINS changes the priority of Secure HardFault */
+ /* BFHFNMINS changes the priority of Secure HardFault, and
+ * allows a pending Non-secure HardFault to preempt (which
+ * we implement by marking it enabled).
+ */
if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -3;
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
} else {
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
}
}
nvic_irq_update(s);
@@ -1566,7 +1571,6 @@ static void armv7m_nvic_reset(DeviceState *dev)
NVICState *s = NVIC(dev);
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
- s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
/* MEM, BUS, and USAGE are enabled through
* the System Handler Control register
*/
@@ -1588,6 +1592,10 @@ static void armv7m_nvic_reset(DeviceState *dev)
/* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;
+ /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 0;
+ } else {
+ s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
}
/* Strictly speaking the reset handler should be enabled.
--
2.7.4
- [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK, (continued)
- [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 05/31] xilinx_axienet: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers, Peter Maydell, 2017/09/07
- Re: [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 01/31] target/arm: Implement MSR/MRS access to NS banked registers, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear,
Peter Maydell <=
- [Qemu-devel] [PULL 12/31] nvic: In escalation to HardFault, support HF not being priority -1, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 16/31] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 11/31] nvic: Compare group priority for escalation to HF, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 13/31] nvic: Implement v8M changes to fixed priority exceptions, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 15/31] nvic: Handle v8M changes in nvic_exec_prio(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 17/31] nvic: Make ICSR banked for v8M, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 10/31] nvic: Make SHPR registers banked, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 08/31] nvic: Handle banked exceptions in nvic_recompute_state(), Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 09/31] nvic: Make set_pending and clear_pending take a secure parameter, Peter Maydell, 2017/09/21
- [Qemu-devel] [PULL 05/31] nvic: Implement AIRCR changes for v8M, Peter Maydell, 2017/09/21