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[Qemu-devel] [PULL 08/17] tcg: Remove tcg_regset_clear
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 08/17] tcg: Remove tcg_regset_clear |
Date: |
Sun, 17 Sep 2017 08:05:26 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.h | 1 -
tcg/aarch64/tcg-target.inc.c | 2 +-
tcg/arm/tcg-target.inc.c | 2 +-
tcg/i386/tcg-target.inc.c | 4 ++--
tcg/mips/tcg-target.inc.c | 2 +-
tcg/ppc/tcg-target.inc.c | 2 +-
tcg/s390/tcg-target.inc.c | 8 ++++----
tcg/sparc/tcg-target.inc.c | 2 +-
tcg/tcg.c | 5 ++---
tcg/tci/tcg-target.inc.c | 2 +-
10 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index e342fe614f..6525e51c21 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -186,7 +186,6 @@ typedef enum TCGOpcode {
NB_OPS,
} TCGOpcode;
-#define tcg_regset_clear(d) (d) = 0
#define tcg_regset_set(d, s) (d) = (s)
#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
#define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index c2f3812214..75d819258e 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1940,7 +1940,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_X16) | (1 << TCG_REG_X17) |
(1 << TCG_REG_X18) | (1 << TCG_REG_X30));
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index db46aea38c..f0c176554b 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2173,7 +2173,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_R12) |
(1 << TCG_REG_R14));
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 5231056fd3..0c19ab7cc2 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2649,7 +2649,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
}
- tcg_regset_clear(tcg_target_call_clobber_regs);
+ tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
@@ -2664,7 +2664,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
}
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
}
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 750baadf37..85c1abd14b 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -2629,7 +2629,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_T8) |
(1 << TCG_REG_T9));
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 3c9355844a..44305ba9e8 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -2788,7 +2788,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_R11) |
(1 << TCG_REG_R12));
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
#if defined(_CALL_SYSV)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e7ab8e4df3..01baa33673 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -413,12 +413,12 @@ static const char
*target_parse_constraint(TCGArgConstraint *ct,
break;
case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG;
- tcg_regset_clear(ct->u.regs);
+ ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG;
- tcg_regset_clear(ct->u.regs);
+ ct->u.regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
break;
case 'A':
@@ -2522,7 +2522,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
- tcg_regset_clear(tcg_target_call_clobber_regs);
+ tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
@@ -2535,7 +2535,7 @@ static void tcg_target_init(TCGContext *s)
/* The return register can be considered call-clobbered. */
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
/* XXX many insns can't be used with R0, so we better avoid it for now */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index bd7c1461c6..ccd83205d5 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1771,7 +1771,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_O5) |
(1 << TCG_REG_O7));
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b65a73208f..9eeaba9529 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1500,7 +1500,7 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL);
- tcg_regset_clear(def->args_ct[i].u.regs);
+ def->args_ct[i].u.regs = 0;
def->args_ct[i].ct = 0;
while (*ct_str != '\0') {
switch(*ct_str) {
@@ -2664,9 +2664,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int
nb_oargs, int nb_iargs,
tcg_out_mov(s, ts->type, reg, ts->reg);
}
} else {
- TCGRegSet arg_set;
+ TCGRegSet arg_set = 0;
- tcg_regset_clear(arg_set);
tcg_regset_set_reg(arg_set, reg);
temp_load(s, ts, arg_set, allocated_regs);
}
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index 94461b2baf..f9644334cc 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -879,7 +879,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
BIT(TCG_TARGET_NB_REGS) - 1);
- tcg_regset_clear(s->reserved_regs);
+ s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
/* We use negative offsets from "sp" so that we can distinguish
--
2.13.5
- [Qemu-devel] [PULL 00/17] TCG queued patches, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 01/17] tcg/ppc: disable atomic write check on ppc32, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 04/17] accel/tcg: move tcg-runtime to accel/tcg/, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 02/17] accel/tcg: move softmmu_template.h to accel/tcg/, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 03/17] accel/tcg: move user-exec to accel/tcg/, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 06/17] accel/tcg: move USER code to user-exec.c, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 05/17] accel/tcg: move atomic_template.h to accel/tcg/, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 07/17] tcg: Add tcg_op_supported, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 10/17] tcg: Remove tcg_regset_{or, and, andnot, not}, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 08/17] tcg: Remove tcg_regset_clear,
Richard Henderson <=
- [Qemu-devel] [PULL 09/17] tcg: Remove tcg_regset_set, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 11/17] tcg: Remove tcg_regset_set32, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 14/17] tcg/arm: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 12/17] tcg: Fix types in tcg_regset_{set, reset}_reg, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 13/17] tcg/aarch64: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 17/17] tcg/mips: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 15/17] tcg/ppc: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/17
- [Qemu-devel] [PULL 16/17] tcg/sparc: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/17
- Re: [Qemu-devel] [PULL 00/17] TCG queued patches, Peter Maydell, 2017/09/17