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[Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers |
Date: |
Tue, 12 Sep 2017 09:25:04 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 98b9b26fd3..419f008277 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -486,7 +486,7 @@ typedef struct CPUARMState {
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
*/
- float64 regs[64];
+ float64 regs[64] __attribute__((aligned(16)));
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
--
2.13.5
- [Qemu-devel] [PATCH v2 00/16] TCG vectorization and example conversion, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 01/16] tcg: Add expanders for out-of-line vector helpers, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 02/16] tcg: Add types for host vectors, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 03/16] tcg: Add operations for host vectors, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 05/16] tcg: Add INDEX_op_invalid, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 04/16] tcg: Add tcg_op_supported, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 06/16] tcg: Add vector infrastructure and ops for add/sub/logic, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 08/16] target/arm: Use vector infrastructure for aa64 add/sub/logic, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 10/16] tcg/aarch64: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/12
- [Qemu-devel] [PATCH v2 12/16] tcg: Remove tcg_regset_set, Richard Henderson, 2017/09/12