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[Qemu-devel] [PULL 36/36] arm_gicv3_kvm: Fix compile warning
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 36/36] arm_gicv3_kvm: Fix compile warning |
Date: |
Mon, 4 Sep 2017 13:26:07 +0100 |
From: Pranith Kumar <address@hidden>
Fix the following warning:
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only
applied to the left hand side of this bitwise operator
[-Wlogical-not-parentheses]
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^ ~
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after
the '!' to evaluate the bitwise operator first
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around
left hand side expression to silence this warning
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
This logic error meant we were not setting the PTZ
bit when we should -- luckily as the comment suggests
this wouldn't have had any effects beyond making GIC
initialization take a little longer.
Signed-off-by: Pranith Kumar <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 6051c77..481fe54 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -293,7 +293,7 @@ static void kvm_arm_gicv3_put(GICv3State *s)
kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true);
reg64 = c->gicr_pendbaser;
- if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
+ if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
/* Setting PTZ is advised if LPIs are disabled, to reduce
* GIC initialization time.
*/
--
2.7.4
- [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages, (continued)
- [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the reset width register, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed() hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 32/36] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 34/36] hw/arm/digic: Mark device with user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 27/36] cputlb: Support generating CPU exceptions on memory transaction failures, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 31/36] target/arm: Allow deliver_fault() caller to specify EA bit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 33/36] hw/arm/aspeed_soc: Mark devices as user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 29/36] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 36/36] arm_gicv3_kvm: Fix compile warning,
Peter Maydell <=
- [Qemu-devel] [PULL 28/36] boards.h: Define new flag ignore_memory_transaction_failures, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 30/36] target/arm: Factor out fault delivery code, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2017/09/04