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[Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_p
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_phys_addr() |
Date: |
Mon, 4 Sep 2017 13:25:34 +0100 |
Currently get_phys_addr() has PMSAv7 handling before the
"is translation disabled?" check, and then PMSAv5 after it.
Tidy this up by making the PMSAv5 code handle the "MPU disabled"
case itself, so that we have all the PMSA code in one place.
This will make adding the PMSAv8 code slightly cleaner, and
also means that pre-v7 PMSA cores benefit from the MPU lookup
logging that the PMSAv7 codepath had.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8e148be..8190682 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8418,6 +8418,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,
uint32_t address,
uint32_t base;
bool is_user = regime_is_user(env, mmu_idx);
+ if (regime_translation_disabled(env, mmu_idx)) {
+ /* MPU disabled. */
+ *phys_ptr = address;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return false;
+ }
+
*phys_ptr = address;
for (n = 7; n >= 0; n--) {
base = env->cp15.c6_region[n];
@@ -8567,16 +8574,20 @@ static bool get_phys_addr(CPUARMState *env,
target_ulong address,
}
}
- /* pmsav7 has special handling for when MPU is disabled so call it before
- * the common MMU/MPU disabled check below.
- */
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
- arm_feature(env, ARM_FEATURE_V7)) {
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
bool ret;
*page_size = TARGET_PAGE_SIZE;
- ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
- phys_ptr, prot, fsr);
- qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
+
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ /* PMSAv7 */
+ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
+ phys_ptr, prot, fsr);
+ } else {
+ /* Pre-v7 MPU */
+ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
+ phys_ptr, prot, fsr);
+ }
+ qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",
access_type == MMU_DATA_LOAD ? "reading" :
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
@@ -8589,21 +8600,16 @@ static bool get_phys_addr(CPUARMState *env,
target_ulong address,
return ret;
}
+ /* Definitely a real MMU, not an MPU */
+
if (regime_translation_disabled(env, mmu_idx)) {
- /* MMU/MPU disabled. */
+ /* MMU disabled. */
*phys_ptr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
*page_size = TARGET_PAGE_SIZE;
return 0;
}
- if (arm_feature(env, ARM_FEATURE_PMSA)) {
- /* Pre-v7 MPU */
- *page_size = TARGET_PAGE_SIZE;
- return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
- phys_ptr, prot, fsr);
- }
-
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
attrs, prot, page_size, fsr, fi);
--
2.7.4
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 05/36] hw/intc/armv7m_nvic.c: Remove out of date comment, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where new v8M insns will be, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_phys_addr(),
Peter Maydell <=
- [Qemu-devel] [PULL 06/36] target/arm: Remove incorrect comment about MPU_CTRL, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 07/36] target/arm: Fix outdated comment about exception exit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 01/36] target/arm: Use MMUAccessType enum rather than int, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 02/36] target/arm: Don't trap WFI/WFE for M profile, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), Peter Maydell, 2017/09/04