[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH for-2.11 18/23] tcg/arm: Extract INSN_NOP
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-2.11 18/23] tcg/arm: Extract INSN_NOP |
Date: |
Thu, 3 Aug 2017 22:44:21 -0700 |
We'll want this for tcg_out_nop_fill.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/arm/tcg-target.inc.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index f40e87066f..78603a19db 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -160,8 +160,18 @@ typedef enum {
INSN_DMB_ISH = 0x5bf07ff5,
INSN_DMB_MCR = 0xba0f07ee,
+
+ /* Architected nop introduced in v6k. */
+ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
+ also Just So Happened to do nothing on pre-v6k so that we
+ don't need to conditionalize it? */
+ INSN_NOP_v6k = 0xe320f000,
+ /* Otherwise the assembler uses mov r0,r0 */
+ INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
} ARMInsn;
+#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
+
static const uint8_t tcg_cond_to_arm_cond[] = {
[TCG_COND_EQ] = COND_EQ,
[TCG_COND_NE] = COND_NE,
@@ -375,16 +385,7 @@ static inline void tcg_out_dat_reg(TCGContext *s,
static inline void tcg_out_nop(TCGContext *s)
{
- if (use_armv7_instructions) {
- /* Architected nop introduced in v6k. */
- /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
- also Just So Happened to do nothing on pre-v6k so that we
- don't need to conditionalize it? */
- tcg_out32(s, 0xe320f000);
- } else {
- /* Prior to that the assembler uses mov r0, r0. */
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));
- }
+ tcg_out32(s, INSN_NOP);
}
static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
--
2.13.3
- [Qemu-devel] [PATCH for-2.11 07/23] tcg/s390: Use constant pool for movi, (continued)
- [Qemu-devel] [PATCH for-2.11 07/23] tcg/s390: Use constant pool for movi, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 10/23] tcg/s390: Use constant pool for xori, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 12/23] tcg/aarch64: Use constant pool for movi, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 11/23] tcg/s390: Use constant pool for cmpi, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 13/23] tcg/sparc: Introduce TCG_REG_TB, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 16/23] tcg/arm: Tighten tlb indexing offset test, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 09/23] tcg/s390: Use constant pool for ori, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 15/23] tcg/arm: Improve tlb load for armv7, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 14/23] tcg/sparc: Use constant pool for movi, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 20/23] tcg/arm: Use constant pool for call, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 18/23] tcg/arm: Extract INSN_NOP,
Richard Henderson <=
- [Qemu-devel] [PATCH for-2.11 19/23] tcg/arm: Use constant pool for movi, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 17/23] tcg/arm: Code rearrangement, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 22/23] tcg/ppc: Look for shifted constants, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 21/23] tcg/ppc: Change TCG_REG_RA to TCG_REG_TB, Richard Henderson, 2017/08/04
- [Qemu-devel] [PATCH for-2.11 23/23] tcg/ppc: Use constant pool for movi, Richard Henderson, 2017/08/04