Re: [Qemu-devel] [PATCH 3/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes

[Yongbok Kim]

On 18/07/2017 12:55, James Hogan wrote:
> There is no need to invalidate any shadow TLB entries when the ASID
> changes or when access to one of the 64-bit segments has been disabled,
> since doing so doesn't reveal to software whether any TLB entries have
> been evicted into the shadow half of the TLB.
> 
> Therefore weaken the tlb flushes in these cases to only flush the QEMU
> TLB.
> 
> Signed-off-by: James Hogan <address@hidden>
> Cc: Yongbok Kim <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
> ---
> Changes in v2:
> - New patch.
> ---
>  target/mips/helper.c    | 2 +-
>  target/mips/op_helper.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index e359ca3b448d..ceaeb8ceaf49 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, 
> target_ulong val)
>  #if defined(TARGET_MIPS64)
>      if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
>          /* Access to at least one of the 64-bit segments has been disabled */
> -        cpu_mips_tlb_flush(env);
> +        tlb_flush(CPU(mips_env_get_cpu(env)));
>      }
>  #endif
>      if (env->CP0_Config3 & (1 << CP0C3_MT)) {
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 1961cacfab18..c07f68ce1a97 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -1416,7 +1416,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, 
> target_ulong arg1)
>      /* If the ASID changes, flush qemu's TLB.  */
>      if ((old & env->CP0_EntryHi_ASID_mask) !=
>          (val & env->CP0_EntryHi_ASID_mask)) {
> -        cpu_mips_tlb_flush(env);
> +        tlb_flush(CPU(mips_env_get_cpu(env)));
>      }
>  }
>  
> 

Tested-by: Yongbok Kim <address@hidden>

Regards,
Yongbok