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[Qemu-devel] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvS
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvSIMD scalar 2 register misc decode |
Date: |
Thu, 20 Jul 2017 16:04:18 +0100 |
This is the initial decode skeleton for the Advanced SIMD scalar two
register miscellaneous FP16 instruction group. The fprintfs are to aid
debugging as the additional instructions are added. They will be removed
once the group is complete.
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/translate-a64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a8876e4bcc..c3f6080ce4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10582,6 +10582,65 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
}
+/* ARMv8.2 AdvSIMD two reg misc half-precision
+ *
+ * 31 30 29 28 24 23 17 16 12 11 10 9 5 4 0
+ * +---+---+---+-----------+---+---------------+--------+-----+------+------+
+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 1 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
+ * +---+---+---+-----------+---+---------------+--------+-----+------+------+
+ *
+ * This includes conversion functions and compare against zero
+ */
+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+{
+ int opcode = extract32(insn, 12, 5);
+ int u = extract32(insn, 29, 1);
+ int is_q = extract32(insn, 30, 1);
+ int a = extract32(insn, 23, 1);
+ int rn = extract32(insn, 5, 5);
+ int rd = extract32(insn, 0, 5);
+ int datasize, elements;
+ int fpopcode, pass;
+ TCGv_ptr fpst;
+
+ /* Handle any non-vector operations first */
+ switch (opcode) {
+ default:
+ fprintf(stderr, "%s: not a non-vector opcode %#x\n", __func__, opcode);
+ break;
+ }
+
+ fpopcode = opcode | (a << 5) | (u << 6);
+ datasize = is_q ? 128 : 64;
+ elements = datasize / 16;
+
+ fpst = get_fpstatus_ptr();
+
+ for (pass = 0; pass < elements; pass++) {
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
+
+ switch (fpopcode) {
+ default:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn,
fpopcode);
+ unsupported_encoding(s, insn);
+ }
+
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i32(tcg_op1);
+ }
+
+ tcg_temp_free_ptr(fpst);
+
+ if (!is_q) {
+ /* non-quad vector op */
+ clear_vec_high(s, rd);
+ }
+}
+
/* C3.6.13 AdvSIMD scalar x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
@@ -11259,6 +11318,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
+ { 0x0e780800, 0x9f7f0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
--
2.13.0
- [Qemu-devel] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, (continued)
- [Qemu-devel] [RFC PATCH for 2.11 13/23] target/arm/translate-a64.c: add FP16 FADD to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 08/23] target-aarch64: enable SoftFloat3 build for FP16, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 11/23] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 04/23] softfloat3c: fixup include paths, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvSIMD scalar 2 register misc decode,
Alex Bennée <=
- [Qemu-devel] [RFC PATCH for 2.11 22/23] fpu/softfloat2a: improve comments on ARM NaN propagation, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 23/23] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 18/23] fpu/softfloat2a: implement float16_squash_input_denormal, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 14/23] target/arm/translate-a64.c: add ARMv8.2 fadd scalar half-precision, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 19/23] fpu/softfloat2a: implement float16_abs helper, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 21/23] fpu/softfloat2a: propagate signalling NaNs in MINMAX, Alex Bennée, 2017/07/20