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[Qemu-devel] [PATCH v3 20/43] tcg: check CF_PARALLEL instead of parallel
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [PATCH v3 20/43] tcg: check CF_PARALLEL instead of parallel_cpus |
Date: |
Wed, 19 Jul 2017 23:09:06 -0400 |
Thereby decoupling the resulting translated code from the current state
of the system.
The tb->cflags field is not passed to tcg generation functions. So
we add a bit to TCGContext, storing there whether CF_PARALLEL is set
before translating every TB.
Most architectures have <= 32 registers, which results in a 4-byte hole
in TCGContext. Use this hole for the bit we need, which we store in a bool.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
---
tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 1 +
tcg/tcg-op.c | 10 +++++-----
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 96872f8..9b6dade 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -656,6 +656,7 @@ struct TCGContext {
uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP
*/
TCGRegSet reserved_regs;
+ bool cf_parallel; /* whether CF_PARALLEL is set in tb->cflags */
intptr_t current_frame_offset;
intptr_t frame_start;
intptr_t frame_end;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 600c0a1..645bc70 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1271,6 +1271,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->flags = flags;
tb->cflags = cflags;
tb->trace_vcpu_dstate = *cpu->trace_dstate;
+ tcg_ctx.cf_parallel = !!(cflags & CF_PARALLEL);
#ifdef CONFIG_PROFILER
tcg_ctx.tb_count1++; /* includes aborted translations because of
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 205d07f..ef420d4 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -150,7 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1,
TCGArg a2,
void tcg_gen_mb(TCGBar mb_type)
{
- if (parallel_cpus) {
+ if (tcg_ctx.cf_parallel) {
tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type);
}
}
@@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr,
TCGv_i32 cmpv,
{
memop = tcg_canonicalize_memop(memop, 0, 0);
- if (!parallel_cpus) {
+ if (!tcg_ctx.cf_parallel) {
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr,
TCGv_i64 cmpv,
{
memop = tcg_canonicalize_memop(memop, 1, 0);
- if (!parallel_cpus) {
+ if (!tcg_ctx.cf_parallel) {
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] = {
\
void tcg_gen_atomic_##NAME##_i32 \
(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.cf_parallel) { \
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
@@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32
\
void tcg_gen_atomic_##NAME##_i64 \
(TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
{ \
- if (parallel_cpus) { \
+ if (tcg_ctx.cf_parallel) { \
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
} else { \
do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \
--
2.7.4
- Re: [Qemu-devel] [PATCH v3 17/43] target/s390x: check CF_PARALLEL instead of parallel_cpus, (continued)
- [Qemu-devel] [PATCH v3 34/43] gen-icount: fold exitreq_label into TCGContext, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 09/43] tcg: consolidate TB lookups in tb_lookup__cpu_state, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 11/43] tcg: define CF_PARALLEL and use it for TB hashing, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 37/43] tcg: distribute profiling counters across TCGContext's, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 10/43] exec-all: bring tb->invalid into tb->cflags, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 35/43] tcg: dynamically allocate optimizer temps, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 33/43] tcg: define tcg_init_ctx and make tcg_ctx a pointer, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 13/43] target/arm: check CF_PARALLEL instead of parallel_cpus, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 20/43] tcg: check CF_PARALLEL instead of parallel_cpus,
Emilio G. Cota <=
- [Qemu-devel] [PATCH v3 18/43] target/sh4: check CF_PARALLEL instead of parallel_cpus, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 21/43] cpu-exec: lookup/generate TB outside exclusive region during step_atomic, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 40/43] translate-all: use qemu_protect_rwx/none helpers, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 43/43] tcg: enable multiple TCG contexts in softmmu, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 38/43] util: move qemu_real_host_page_size/mask to osdep.h, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 27/43] translate-all: use a binary search tree to track TBs in TBContext, Emilio G. Cota, 2017/07/19
- [Qemu-devel] [PATCH v3 42/43] tcg: introduce regions to split code_gen_buffer, Emilio G. Cota, 2017/07/19