[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quanti
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities |
Date: |
Tue, 18 Jul 2017 10:02:41 -1000 |
This enforces proper alignment and makes the register update
more natural. Note that there is a more serious bug fix for
fmov {DX}Rn,@(R0,Rn) to use a store instead of a load.
Signed-off-by: Richard Henderson <address@hidden>
---
V2: Fix pre-dec address error.
---
target/sh4/translate.c | 75 ++++++++++++++++++++++++--------------------------
1 file changed, 36 insertions(+), 39 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 9c320e4..bda6fa7 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -998,12 +998,10 @@ static void _decode_opc(DisasContext * ctx)
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
- TCGv addr_hi = tcg_temp_new();
- int fr = XHACK(B7_4);
- tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL);
- tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
- tcg_temp_free(addr_hi);
+ TCGv_i64 fp = tcg_temp_new_i64();
+ gen_load_fpr64(ctx, fp, XHACK(B7_4));
+ tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEQ);
+ tcg_temp_free_i64(fp);
} else {
tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
}
@@ -1011,12 +1009,10 @@ static void _decode_opc(DisasContext * ctx)
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
- TCGv addr_hi = tcg_temp_new();
- int fr = XHACK(B11_8);
- tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
- tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
- tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
- tcg_temp_free(addr_hi);
+ TCGv_i64 fp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ);
+ gen_store_fpr64(ctx, fp, XHACK(B11_8));
+ tcg_temp_free_i64(fp);
} else {
tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
}
@@ -1024,13 +1020,11 @@ static void _decode_opc(DisasContext * ctx)
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
- TCGv addr_hi = tcg_temp_new();
- int fr = XHACK(B11_8);
- tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
- tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
- tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
- tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
- tcg_temp_free(addr_hi);
+ TCGv_i64 fp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ);
+ gen_store_fpr64(ctx, fp, XHACK(B11_8));
+ tcg_temp_free_i64(fp);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
} else {
tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1038,18 +1032,21 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
- TCGv addr = tcg_temp_new_i32();
- tcg_gen_subi_i32(addr, REG(B11_8), 4);
- if (ctx->tbflags & FPSCR_SZ) {
- int fr = XHACK(B7_4);
- tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
- tcg_gen_subi_i32(addr, addr, 4);
- tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
- } else {
- tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
- }
- tcg_gen_mov_i32(REG(B11_8), addr);
- tcg_temp_free(addr);
+ {
+ TCGv addr = tcg_temp_new_i32();
+ if (ctx->tbflags & FPSCR_SZ) {
+ TCGv_i64 fp = tcg_temp_new_i64();
+ gen_load_fpr64(ctx, fp, XHACK(B7_4));
+ tcg_gen_subi_i32(addr, REG(B11_8), 8);
+ tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ);
+ tcg_temp_free_i64(fp);
+ } else {
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
+ }
+ tcg_gen_mov_i32(REG(B11_8), addr);
+ tcg_temp_free(addr);
+ }
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
CHECK_FPU_ENABLED
@@ -1057,10 +1054,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->tbflags & FPSCR_SZ) {
- int fr = XHACK(B11_8);
- tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
- tcg_gen_addi_i32(addr, addr, 4);
- tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
+ TCGv_i64 fp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEQ);
+ gen_store_fpr64(ctx, fp, XHACK(B11_8));
+ tcg_temp_free_i64(fp);
} else {
tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEUL);
}
@@ -1073,10 +1070,10 @@ static void _decode_opc(DisasContext * ctx)
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->tbflags & FPSCR_SZ) {
- int fr = XHACK(B7_4);
- tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
- tcg_gen_addi_i32(addr, addr, 4);
- tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
+ TCGv_i64 fp = tcg_temp_new_i64();
+ gen_load_fpr64(ctx, fp, XHACK(B7_4));
+ tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ);
+ tcg_temp_free_i64(fp);
} else {
tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
}
--
2.9.4
- [Qemu-devel] [PATCH v3 04/30] target/sh4: Keep env->flags clean, (continued)
- [Qemu-devel] [PATCH v3 04/30] target/sh4: Keep env->flags clean, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 05/30] target/sh4: Adjust TB_FLAG_PENDING_MOVCA, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 06/30] target/sh4: Handle user-space atomics, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 07/30] target/sh4: Recognize common gUSA sequences, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 08/30] linux-user/sh4: Notice gUSA regions during signal delivery, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 09/30] linux-user/sh4: Clean env->flags on signal boundaries, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 10/30] target/sh4: Hoist register bank selection, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 12/30] target/sh4: Pass DisasContext to fpr64 routines, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 11/30] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 14/30] target/sh4: Eliminate unused XREG macro, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 17/30] target/sh4: Simplify 64-bit fp reg-reg move, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 18/30] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 15/30] target/sh4: Merge DREG into fpr64 routines, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 19/30] target/sh4: Unify code for CHECK_PRIVILEGED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 20/30] target/sh4: Unify code for CHECK_FPU_ENABLED, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 21/30] target/sh4: Tidy misc illegal insn checks, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 22/30] target/sh4: Introduce CHECK_FPSCR_PR_*, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 24/30] target/sh4: Implement fpchg, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 23/30] target/sh4: Introduce CHECK_SH4A, Richard Henderson, 2017/07/18
- [Qemu-devel] [PATCH v3 25/30] target/sh4: Add missing FPSCR.PR == 0 checks, Richard Henderson, 2017/07/18