[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 1/2] target/mips: fix msa copy_[s|u]_df rd = 0 corner
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 1/2] target/mips: fix msa copy_[s|u]_df rd = 0 corner case |
Date: |
Tue, 11 Jul 2017 16:16:04 +0100 |
From: Miodrag Dinic <address@hidden>
This patch fixes the msa copy_[s|u]_df instruction emulation when
the destination register rd is zero. Without this patch the zero
register would get clobbered, which should never happen because it
is supposed to be hardwired to 0.
Fix this corner case by explicitly checking rd = 0 and effectively
making these instructions emulation no-op in that case.
Signed-off-by: Miodrag Dinic <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Acked-by: Aurelien Jarno <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 559f8fe..befb87f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18712,10 +18712,14 @@ static void gen_msa_elm_df(CPUMIPSState *env,
DisasContext *ctx, uint32_t df,
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
- gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ if (likely(wd != 0)) {
+ gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ }
break;
case OPC_COPY_U_df:
- gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ if (likely(wd != 0)) {
+ gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ }
break;
case OPC_INSERT_df:
gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
--
2.7.4