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[Qemu-devel] [PULL 2/4] aspeed: Register all watchdogs
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 2/4] aspeed: Register all watchdogs |
Date: |
Tue, 11 Jul 2017 11:29:10 +0100 |
From: Joel Stanley <address@hidden>
The ast2400 contains two and the ast2500 contains three watchdogs.
Add this information to the AspeedSoCInfo and realise the correct number
of watchdogs for that each SoC type.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/aspeed_soc.h | 4 +++-
hw/arm/aspeed_soc.c | 25 +++++++++++++++++--------
2 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 4c5fc66..0b88baa 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -23,6 +23,7 @@
#include "hw/net/ftgmac100.h"
#define ASPEED_SPIS_NUM 2
+#define ASPEED_WDTS_NUM 3
typedef struct AspeedSoCState {
/*< private >*/
@@ -39,7 +40,7 @@ typedef struct AspeedSoCState {
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
AspeedSDMCState sdmc;
- AspeedWDTState wdt;
+ AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100;
} AspeedSoCState;
@@ -56,6 +57,7 @@ typedef struct AspeedSoCInfo {
const hwaddr *spi_bases;
const char *fmc_typename;
const char **spi_typename;
+ int wdts_num;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 4937e2b..3034849 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -62,6 +62,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spi_bases = aspeed_soc_ast2400_spi_bases,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+ .wdts_num = 2,
}, {
.name = "ast2400-a1",
.cpu_model = "arm926",
@@ -72,6 +73,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spi_bases = aspeed_soc_ast2400_spi_bases,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+ .wdts_num = 2,
}, {
.name = "ast2400",
.cpu_model = "arm926",
@@ -82,6 +84,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spi_bases = aspeed_soc_ast2400_spi_bases,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+ .wdts_num = 2,
}, {
.name = "ast2500-a1",
.cpu_model = "arm1176",
@@ -92,6 +95,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spi_bases = aspeed_soc_ast2500_spi_bases,
.fmc_typename = "aspeed.smc.ast2500-fmc",
.spi_typename = aspeed_soc_ast2500_typenames,
+ .wdts_num = 3,
},
};
@@ -175,9 +179,11 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size", &error_abort);
- object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
- object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
- qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
+ for (i = 0; i < sc->info->wdts_num; i++) {
+ object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
+ object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
+ qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
+ }
object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
@@ -300,12 +306,15 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
/* Watch dog */
- object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
+ for (i = 0; i < sc->info->wdts_num; i++) {
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
+ ASPEED_SOC_WDT_BASE + i * 0x20);
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
/* Net */
qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
--
2.7.4
- [Qemu-devel] [PULL 0/4] target-arm queue, Peter Maydell, 2017/07/11
- [Qemu-devel] [PULL 0/4] target-arm queue, Peter Maydell, 2017/07/24
- [Qemu-devel] [PULL 1/4] target/arm: fix TCG temp leak in aarch64 rev16, Peter Maydell, 2017/07/24
- [Qemu-devel] [PULL 4/4] integratorcp: Don't migrate flash using vmstate_register_ram_global(), Peter Maydell, 2017/07/24
- [Qemu-devel] [PULL 3/4] mps2: Correctly set parent bus for SCC device, Peter Maydell, 2017/07/24
- [Qemu-devel] [PULL 2/4] fsl_imx*: Migrate ROM contents, Peter Maydell, 2017/07/24
- Re: [Qemu-devel] [PULL 0/4] target-arm queue, Peter Maydell, 2017/07/24