[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals
From: |
Lluís Vilanova |
Subject: |
[Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals |
Date: |
Wed, 28 Jun 2017 16:25:14 +0300 |
User-agent: |
StGit/0.17.1-dirty |
Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <address@hidden>
---
target/arm/translate.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 23a07fc2c6..fc28cd45f7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11843,6 +11843,18 @@ static void
arm_trblock_init_disas_context(DisasContextBase *dcbase,
dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
}
+static void arm_trblock_init_globals(DisasContextBase *dcbase, CPUState *cpu)
+{
+ cpu_F0s = tcg_temp_new_i32();
+ cpu_F1s = tcg_temp_new_i32();
+ cpu_F0d = tcg_temp_new_i64();
+ cpu_F1d = tcg_temp_new_i64();
+ cpu_V0 = cpu_F0d;
+ cpu_V1 = cpu_F1d;
+ /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
+ cpu_M0 = tcg_temp_new_i64();
+}
+
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
@@ -11871,14 +11883,7 @@ void gen_intermediate_code(CPUState *cpu,
TranslationBlock *tb)
arm_trblock_init_disas_context(&dc->base, cpu);
- cpu_F0s = tcg_temp_new_i32();
- cpu_F1s = tcg_temp_new_i32();
- cpu_F0d = tcg_temp_new_i64();
- cpu_F1d = tcg_temp_new_i64();
- cpu_V0 = cpu_F0d;
- cpu_V1 = cpu_F1d;
- /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
- cpu_M0 = tcg_temp_new_i64();
+ arm_trblock_init_globals(&dc->base, cpu);
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) +
TARGET_PAGE_SIZE;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
- [Qemu-devel] [PATCH v11 07/29] target/i386: [tcg] Refactor init_globals, (continued)
- [Qemu-devel] [PATCH v11 07/29] target/i386: [tcg] Refactor init_globals, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 08/29] target/i386: [tcg] Refactor insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 09/29] target/i386: [tcg] Refactor breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 10/29] target/i386: [tcg] Refactor translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 11/29] target/i386: [tcg] Refactor tb_stop, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 12/29] target/i386: [tcg] Refactor disas_log, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 13/29] target/i386: [tcg] Port to generic translation framework, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 14/29] target/arm: [tcg] Port to DisasContextBase, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 15/29] target/arm: [tcg] Port to init_disas_context, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas_context, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 17/29] target/arm: [tcg] Port to init_globals,
Lluís Vilanova <=
- [Qemu-devel] [PATCH v11 18/29] target/arm: [tcg] Port to tb_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 19/29] target/arm: [tcg] Port to insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 20/29] target/arm: [tcg, a64] Port to insn_start, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 21/29] target/arm: [tcg] Port to breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 22/29] target/arm: [tcg, a64] Port to breakpoint_check, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 23/29] target/arm: [tcg] Port to translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 24/29] target/arm: [tcg, a64] Port to translate_insn, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 25/29] target/arm: [tcg] Port to tb_stop, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 26/29] target/arm: [tcg, a64] Port to tb_stop, Lluís Vilanova, 2017/06/28
- [Qemu-devel] [PATCH v11 27/29] target/arm: [tcg] Port to disas_log, Lluís Vilanova, 2017/06/28