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[Qemu-devel] [PATCH v1 2/8] target-microblaze: Don't hard code 0xb as in
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 2/8] target-microblaze: Don't hard code 0xb as initial MB version |
Date: |
Tue, 20 Jun 2017 17:51:20 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Don't hard code 0xb as initial MB version.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index af70faa..4bc77df 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -152,8 +152,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR0_USE_HW_MUL_MASK \
| PVR0_USE_EXC_MASK \
| PVR0_USE_ICACHE_MASK \
- | PVR0_USE_DCACHE_MASK \
- | (0xb << 8);
+ | PVR0_USE_DCACHE_MASK;
env->pvr.regs[2] = PVR2_D_OPB_MASK \
| PVR2_D_LMB_MASK \
| PVR2_I_OPB_MASK \
--
2.7.4
- [Qemu-devel] [PATCH v1 0/8] target-microblaze: Misc configurability, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 2/8] target-microblaze: Don't hard code 0xb as initial MB version,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 1/8] target-microblaze: Correct bit shift for the PVR0 version field, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 3/8] target-microblaze: Add CPU versions 9.4, 9.5 and 9.6, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 5/8] target-microblaze: Introduce a use-div property, Edgar E. Iglesias, 2017/06/20
- [Qemu-devel] [PATCH v1 4/8] target-microblaze: Introduce a use-barrel property, Edgar E. Iglesias, 2017/06/20