[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE |
Date: |
Wed, 10 May 2017 17:01:07 +1000 |
From: Suraj Jitindar Singh <address@hidden>
The UPRT and GTSE bits are set when a guest calls H_REGISTER_PROCESS_TABLE
to choose determine how address translation is performed. Currently these
bits in the LPCR are only set for the cpu which handles the H_CALL, however
they need to be set for all cpus for that guest as address translation
cannot be performed differently on a per cpu basis.
Update the H_CALL handler to set these bits in the LPCR correctly for all
cpus of the guest.
Note it is the reponsibility of the guest to ensure that any secondary cpus
are suspended when the H_CALL is made and thus we can safely update these
values here.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_hcall.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 9f18f75..0d608d6 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -936,7 +936,7 @@ static target_ulong h_register_process_table(PowerPCCPU
*cpu,
target_ulong opcode,
target_ulong *args)
{
- CPUPPCState *env = &cpu->env;
+ CPUState *cs;
target_ulong flags = args[0];
target_ulong proc_tbl = args[1];
target_ulong page_size = args[2];
@@ -992,16 +992,12 @@ static target_ulong h_register_process_table(PowerPCCPU
*cpu,
spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
spapr->patb_entry = cproc; /* Save new process table */
- if ((flags & FLAG_RADIX) || (flags & FLAG_HASH_PROC_TBL)) {
- /* Use Process TBL */
- env->spr[SPR_LPCR] |= LPCR_UPRT;
- } else {
- env->spr[SPR_LPCR] &= ~LPCR_UPRT;
- }
- if (flags & FLAG_GTSE) { /* Partition Uses Guest Translation Shootdwn */
- env->spr[SPR_LPCR] |= LPCR_GTSE;
- } else {
- env->spr[SPR_LPCR] &= ~LPCR_GTSE;
+
+ /* Update the UPRT and GTSE bits in the LPCR for all cpus */
+ CPU_FOREACH(cs) {
+ set_spr(cs, SPR_LPCR, LPCR_UPRT | LPCR_GTSE,
+ ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) |
+ ((flags & FLAG_GTSE) ? LPCR_GTSE : 0));
}
if (kvm_enabled()) {
--
2.9.3
- [Qemu-devel] [PULL 09/22] ppc/xics: preserve P and Q bits for KVM IRQs, (continued)
- [Qemu-devel] [PULL 09/22] ppc/xics: preserve P and Q bits for KVM IRQs, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 10/22] Add QemuMacDrivers as submodule, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 12/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 07/22] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 22/22] pnv: Fix build failures on some host platforms, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built as submodule, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE,
David Gibson <=
- [Qemu-devel] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 01/22] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 19/22] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 17/22] target/ppc: Implement ISA V3.00 radix page fault handler, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 20/22] spapr: Don't accidentally advertise HTM support on POWER9, David Gibson, 2017/05/10
- Re: [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510, no-reply, 2017/05/10