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[Qemu-devel] [PULL 03/11] target/openrisc: Implement EPH bit
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 03/11] target/openrisc: Implement EPH bit |
Date: |
Mon, 1 May 2017 08:14:17 +0900 |
From: Tim 'mithro' Ansell <address@hidden>
Exception Prefix High (EPH) control bit of the Supervision Register
(SR).
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
If SR[EPH] is set, the vector offset is logically ORed with the offset
0xF0000000.
This means if EPH is;
* 0 - Exceptions vectors start at EVBAR
* 1 - Exception vectors start at EVBAR | 0xF0000000
Signed-off-by: Tim 'mithro' Ansell <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/interrupt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 78f0ba9..2c91fab 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
if (env->cpucfgr & CPUCFGR_EVBARP) {
vect_pc |= env->evbar;
}
+ if (env->sr & SR_EPH) {
+ vect_pc |= 0xf0000000;
+ }
env->pc = vect_pc;
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
--
2.9.3
- [Qemu-devel] [PULL 00/11] Fixes and features for OpenRISC, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 01/11] MAINTAINERS: Add myself as openrisc maintainer, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 02/11] target/openrisc: Implement EVBAR register, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 03/11] target/openrisc: Implement EPH bit,
Stafford Horne <=
- [Qemu-devel] [PULL 04/11] target/openrisc: Fixes for memory debugging, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 05/11] target/openrisc: add numcores and coreid support, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 06/11] migration: Add VMSTATE_UINTTL_2DARRAY(), Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 08/11] migration: Add VMSTATE_STRUCT_2DARRAY(), Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 07/11] target/openrisc: implement shadow registers, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 09/11] target/openrisc: Implement full vmstate serialization, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 10/11] target/openrisc: Remove duplicate features property, Stafford Horne, 2017/04/30
- [Qemu-devel] [PULL 11/11] target/openrisc: Support non-busy idle state using PMR SPR, Stafford Horne, 2017/04/30
- Re: [Qemu-devel] [PULL 00/11] Fixes and features for OpenRISC, no-reply, 2017/04/30