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[Qemu-devel] [PULL 25/48] ppc/pnv: add a helper to calculate MMIO addres
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 25/48] ppc/pnv: add a helper to calculate MMIO addresses registers |
Date: |
Wed, 26 Apr 2017 17:00:11 +1000 |
From: Cédric Le Goater <address@hidden>
Some controllers (ICP, PSI) have a base register address which is
calculated using the chip id.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
include/hw/ppc/pnv.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index df98a72..5693ba1 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -91,14 +91,24 @@ typedef struct PnvChipClass {
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
/*
- * This generates a HW chip id depending on an index:
+ * This generates a HW chip id depending on an index, as found on a
+ * two socket system with dual chip modules :
*
* 0x0, 0x1, 0x10, 0x11
*
* 4 chips should be the maximum
+ *
+ * TODO: use a machine property to define the chip ids
*/
#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
+/*
+ * Converts back a HW chip id to an index. This is useful to calculate
+ * the MMIO addresses of some controllers which depend on the chip id.
+ */
+#define PNV_CHIP_INDEX(chip) \
+ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+
#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define POWERNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
--
2.9.3
- [Qemu-devel] [PULL 09/48] target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL, (continued)
- [Qemu-devel] [PULL 09/48] target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 16/48] target/ppc: Add ibm, processor-radix-AP-encodings for TCG, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 14/48] spapr_pci: Warn when RAM page size is not enabled in IOMMU page mask, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 13/48] target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 20/48] ppc/xics: add a realize() handler to ICPStateClass, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 23/48] ppc/pnv: extend the machine with a InterruptStatsProvider interface, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 22/48] ppc/pnv: extend the machine with a XICSFabric interface, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 19/48] spapr: allocate the ICPState object from under sPAPRCPUCore, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 10/48] spapr: move spapr_populate_pa_features(), David Gibson, 2017/04/26
- [Qemu-devel] [PULL 15/48] spapr_pci: Removed unused include, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 25/48] ppc/pnv: add a helper to calculate MMIO addresses registers,
David Gibson <=
- [Qemu-devel] [PULL 33/48] ipmi: introduce an ipmi_bmc_gen_event() API, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 12/48] spapr: Workaround for broken radix guests, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 24/48] ppc/pnv: create the ICP object under PnvCore, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 21/48] ppc/pnv: add a PnvICPState object, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 26/48] ppc/pnv: add memory regions for the ICP registers, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 30/48] ipmi: use a file to load SDRs, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 31/48] ipmi: provide support for FRUs, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 39/48] ppc/pnv: populate device tree for RTC devices, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 28/48] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/26
- [Qemu-devel] [PULL 41/48] ppc/pnv: populate device tree for IPMI BT devices, David Gibson, 2017/04/26