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[Qemu-devel] [PULL 25/47] ppc/pnv: add a helper to calculate MMIO addres
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 25/47] ppc/pnv: add a helper to calculate MMIO addresses registers |
Date: |
Mon, 24 Apr 2017 11:59:05 +1000 |
From: Cédric Le Goater <address@hidden>
Some controllers (ICP, PSI) have a base register address which is
calculated using the chip id.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
include/hw/ppc/pnv.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index df98a72..5693ba1 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -91,14 +91,24 @@ typedef struct PnvChipClass {
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
/*
- * This generates a HW chip id depending on an index:
+ * This generates a HW chip id depending on an index, as found on a
+ * two socket system with dual chip modules :
*
* 0x0, 0x1, 0x10, 0x11
*
* 4 chips should be the maximum
+ *
+ * TODO: use a machine property to define the chip ids
*/
#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
+/*
+ * Converts back a HW chip id to an index. This is useful to calculate
+ * the MMIO addresses of some controllers which depend on the chip id.
+ */
+#define PNV_CHIP_INDEX(chip) \
+ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+
#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define POWERNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
--
2.9.3
- [Qemu-devel] [PULL 20/47] ppc/xics: add a realize() handler to ICPStateClass, (continued)
- [Qemu-devel] [PULL 20/47] ppc/xics: add a realize() handler to ICPStateClass, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 43/47] ppc/pnv: generate an OEM SEL event on shutdown, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 42/47] ppc/pnv: add initial IPMI sensors for the BMC simulator, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 35/47] spapr: remove the 'nr_servers' field from the machine, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 17/47] ppc/xics: introduce an 'intc' backlink under PowerPCCPU, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 24/47] ppc/pnv: create the ICP object under PnvCore, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 26/47] ppc/pnv: add memory regions for the ICP registers, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 46/47] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 28/47] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 44/47] spapr-cpu-core: Release ICPState object during CPU unrealization, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 25/47] ppc/pnv: add a helper to calculate MMIO addresses registers,
David Gibson <=
- [Qemu-devel] [PULL 22/47] ppc/pnv: extend the machine with a XICSFabric interface, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 41/47] ppc/pnv: populate device tree for IPMI BT devices, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 38/47] ppc/pnv: scan ISA bus to populate device tree, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 33/47] ipmi: introduce an ipmi_bmc_gen_event() API, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 45/47] target/ppc: Flush TLB on write to PIDR, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 34/47] target/ppc: Fix size of struct PPCElfPrstatus, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 37/47] ppc/pnv: enable only one LPC bus, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 31/47] ipmi: provide support for FRUs, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 36/47] ppc/pnv: Add support for POWER8+ LPC Controller, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 39/47] ppc/pnv: populate device tree for RTC devices, David Gibson, 2017/04/23