Re: [Qemu-devel] [PATCH 2/2] target/openrisc: Implement EPH bit

[Stafford Horne]

On Tue, Apr 18, 2017 at 04:15:51PM +1000, Tim 'mithro' Ansell wrote:
> Exception Prefix High (EPH) control bit of the Supervision Register
> (SR).
> 
> The significant bits (31-12) of the vector offset address for each
> exception depend on the setting of the Supervision Register (SR)'s EPH
> bit and the Exception Vector Base Address Register (EVBAR).
> 
> If SR[EPH] is set, the vector offset is logically ORed with the offset
> 0xF0000000.
> 
> This means if EPH is;
>  * 0 - Exceptions vectors start at EVBAR
>  * 1 - Exception vectors start at EVBAR | 0xF0000000
> 
> Signed-off-by: Tim 'mithro' Ansell <address@hidden>

Acked-by: Stafford Horne <address@hidden>

Thanks, I will queue this with my other changes unless anyone has any
objections.

> ---
>  target/openrisc/interrupt.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> index 78f0ba9421..2c91fab380 100644
> --- a/target/openrisc/interrupt.c
> +++ b/target/openrisc/interrupt.c
> @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
>          if (env->cpucfgr & CPUCFGR_EVBARP) {
>              vect_pc |= env->evbar;
>          }
> +        if (env->sr & SR_EPH) {
> +            vect_pc |= 0xf0000000;
> +        }
>          env->pc = vect_pc;
>      } else {
>          cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> -- 
> 2.12.1
>