Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

[Richard Henderson]

On 02/27/2017 10:22 PM, Eric Bischoff wrote:
> From: Eric Bischoff <address@hidden>
>
> LPD = LOAD PAIR DISJOINT
> ---
>  target/s390x/insn-data.def |  4 +++-
>  target/s390x/translate.c   | 21 +++++++++++++++++++++
>  2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index 075ff59..e427988 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -504,7 +504,9 @@
>      C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)
>      C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
>      C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
> -/* LOAD PAIR DISJOINT TODO */
> +/* LOAD PAIR DISJOINT */
> +    C(0xc804, LPD,     SSF,   ILA, m1_32s, m2_32s, 0, r3_P32, movx, zero)
> +    C(0xc805, LPDG,    SSF,   ILA, m1_64, m2_64, 0, r3_P64, movx, zero)

The think is, in order to be able to say that the two loads were interlocked, 
which is what you're doing with CC=0, we need to provide some atomicity.

In general, this is going to require that you check parallel_cpus, and if true, 
signal cpu_loop_exit_atomic.

As a special case, it would be possible to check for two loads that happen to 
be sequential and perform them as an atomic read.  Whether that happens often 
enough to be worthwhile I don't know.


r~