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[Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zer
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero() |
Date: |
Wed, 22 Feb 2017 17:33:29 +1100 |
From: Bharata B Rao <address@hidden>
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction
of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
fpu/softfloat.c | 28 ++++++++++++++++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 47e4646..485a006 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6188,6 +6188,34 @@ uint64_t float128_to_uint64_round_to_zero(float128 a,
float_status *status)
/*----------------------------------------------------------------------------
| Returns the result of converting the quadruple-precision floating-point
+| value `a' to the 32-bit unsigned integer format. The conversion
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic except that the conversion is always rounded toward zero.
+| If `a' is a NaN, the largest positive integer is returned. Otherwise,
+| if the conversion overflows, the largest unsigned integer is returned.
+| If 'a' is negative, the value is rounded and zero is returned; negative
+| values that do not round to zero will raise the inexact exception.
+*----------------------------------------------------------------------------*/
+
+uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *status)
+{
+ uint64_t v;
+ uint32_t res;
+ int old_exc_flags = get_float_exception_flags(status);
+
+ v = float128_to_uint64_round_to_zero(a, status);
+ if (v > 0xffffffff) {
+ res = 0xffffffff;
+ } else {
+ return v;
+ }
+ set_float_exception_flags(old_exc_flags, status);
+ float_raise(float_flag_invalid, status);
+ return res;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the quadruple-precision floating-point
| value `a' to the single-precision floating-point format. The conversion
| is performed according to the IEC/IEEE Standard for Binary Floating-Point
| Arithmetic.
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index a09ad0e..f1288ef 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -716,6 +716,7 @@ int64_t float128_to_int64(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
float64 float128_to_float64(float128, float_status *status);
floatx80 float128_to_floatx80(float128, float_status *status);
--
2.9.3
- [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction, (continued)
- [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 14/43] target-ppc: generate exception for copy/paste, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 04/43] ppc: implement xsrqpi[x] instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 12/43] target-ppc: implement load atomic instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 05/43] ppc: implement xsrqpxp instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 07/43] ppc: implement xssubqp instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 06/43] ppc: implement xssqrtqp instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt(), David Gibson, 2017/02/22
- [Qemu-devel] [PULL 33/43] pc: move pcms->possible_cpus init out of pc_cpus_init(), David Gibson, 2017/02/22
- [Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero(),
David Gibson <=
- [Qemu-devel] [PULL 36/43] change CPUArchId.cpu type to Object*, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 13/43] target-ppc: implement store atomic instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 15/43] target-ppc: add slbieg instruction, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 20/43] ppc4xx: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 19/43] mac99: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-devel] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions, David Gibson, 2017/02/22