[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits |
Date: |
Fri, 10 Feb 2017 18:08:02 +0000 |
From: Cédric Le Goater <address@hidden>
The size of a segment is not necessarily a power of 2.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/aspeed_smc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 7017707..cb51573 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -475,15 +475,15 @@ static uint32_t aspeed_smc_check_segment_addr(const
AspeedSMCFlash *fl,
AspeedSegments seg;
aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
- if ((addr & (seg.size - 1)) != addr) {
+ if ((addr % seg.size) != addr) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid address 0x%08x for CS%d segment : "
"[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
s->ctrl->name, addr, fl->id, seg.addr,
seg.addr + seg.size);
+ addr %= seg.size;
}
- addr &= seg.size - 1;
return addr;
}
--
2.7.4
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength(), Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits,
Peter Maydell <=
- [Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt, Peter Maydell, 2017/02/10
- [Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0, Peter Maydell, 2017/02/10
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2017/02/13