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[Qemu-devel] [PATCH v11 21/24] target-arm: don't generate WFE/YIELD call
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v11 21/24] target-arm: don't generate WFE/YIELD calls for MTTCG |
Date: |
Thu, 9 Feb 2017 17:09:01 +0000 |
The WFE and YIELD instructions are really only hints and in TCG's case
they were useful to move the scheduling on from one vCPU to the next. In
the parallel context (MTTCG) this just causes an unnecessary cpu_exit
and contention of the BQL.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target/arm/op_helper.c | 7 +++++++
target/arm/translate-a64.c | 8 ++++++--
target/arm/translate.c | 20 ++++++++++++++++----
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index e1a883c595..abfa7cdd39 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -436,6 +436,13 @@ void HELPER(yield)(CPUARMState *env)
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
+ /* When running in MTTCG we don't generate jumps to the yield and
+ * WFE helpers as it won't affect the scheduling of other vCPUs.
+ * If we wanted to more completely model WFE/SEV so we don't busy
+ * spin unnecessarily we would need to do something more involved.
+ */
+ g_assert(!parallel_cpus);
+
/* This is a non-trappable hint instruction that generally indicates
* that the guest is currently busy-looping. Yield control back to the
* top level loop so that a more deserving VCPU has a chance to run.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d0352e2045..7e7131fe2f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1342,10 +1342,14 @@ static void handle_hint(DisasContext *s, uint32_t insn,
s->is_jmp = DISAS_WFI;
return;
case 1: /* YIELD */
- s->is_jmp = DISAS_YIELD;
+ if (!parallel_cpus) {
+ s->is_jmp = DISAS_YIELD;
+ }
return;
case 2: /* WFE */
- s->is_jmp = DISAS_WFE;
+ if (!parallel_cpus) {
+ s->is_jmp = DISAS_WFE;
+ }
return;
case 4: /* SEV */
case 5: /* SEVL */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 493c627bcf..24faa7c60c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4345,20 +4345,32 @@ static void gen_exception_return(DisasContext *s,
TCGv_i32 pc)
gen_rfe(s, pc, load_cpu_field(spsr));
}
+/*
+ * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we
+ * only call the helper when running single threaded TCG code to ensure
+ * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
+ * just skip this instruction. Currently the SEV/SEVL instructions
+ * which are *one* of many ways to wake the CPU from WFE are not
+ * implemented so we can't sleep like WFI does.
+ */
static void gen_nop_hint(DisasContext *s, int val)
{
switch (val) {
case 1: /* yield */
- gen_set_pc_im(s, s->pc);
- s->is_jmp = DISAS_YIELD;
+ if (!parallel_cpus) {
+ gen_set_pc_im(s, s->pc);
+ s->is_jmp = DISAS_YIELD;
+ }
break;
case 3: /* wfi */
gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI;
break;
case 2: /* wfe */
- gen_set_pc_im(s, s->pc);
- s->is_jmp = DISAS_WFE;
+ if (!parallel_cpus) {
+ gen_set_pc_im(s, s->pc);
+ s->is_jmp = DISAS_WFE;
+ }
break;
case 4: /* sev */
case 5: /* sevl */
--
2.11.0
- [Qemu-devel] [PATCH v11 11/24] tcg: enable thread-per-vCPU, (continued)
- [Qemu-devel] [PATCH v11 11/24] tcg: enable thread-per-vCPU, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 10/24] tcg: enable tb_lock() for SoftMMU, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 13/24] cputlb: add assert_cpu_is_self checks, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 12/24] tcg: handle EXCP_ATOMIC exception for system emulation, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 08/24] tcg: drop global lock during TCG code execution, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 07/24] tcg: rename tcg_current_cpu to tcg_current_rr_cpu, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 15/24] cputlb: introduce tlb_flush_* async work., Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 16/24] cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 19/24] cputlb: introduce tlb_flush_*_all_cpus[_synced], Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 18/24] cputlb: atomically update tlb fields used by tlb_reset_dirty, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 21/24] target-arm: don't generate WFE/YIELD calls for MTTCG,
Alex Bennée <=
- [Qemu-devel] [PATCH v11 17/24] cputlb: add tlb_flush_by_mmuidx async routines, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 24/24] tcg: enable MTTCG by default for ARM on x86 hosts, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 20/24] target-arm/powerctl: defer cpu reset work to CPU context, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 22/24] target-arm: ensure all cross vCPUs TLB flushes complete, Alex Bennée, 2017/02/09