Re: [Qemu-devel] [PATCH] arm_gicv3: Fix broken logic in ELRSR calculation

[Thomas Huth]

On 24.01.2017 12:06, Peter Maydell wrote:
> Fix a broken expression in the calculation of ELRSR
> register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
> we want to check for != 0, because the HW bit is not
> bit 0 so a test for == 1 is always false.
> 
> Fixes: https://bugs.launchpad.net/bugs/1658506
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/intc/arm_gicv3_cpuif.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index a9ee7fd..c25ee03 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2430,7 +2430,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const 
> ARMCPRegInfo *ri)
>          uint64_t lr = cs->ich_lr_el2[i];
>  
>          if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
> -            ((lr & ICH_LR_EL2_HW) == 1 || (lr & ICH_LR_EL2_EOI) == 0)) {
> +            ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) {
>              value |= (1 << i);
>          }
>      }
> 

Reviewed-by: Thomas Huth <address@hidden>