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[Qemu-devel] [PULL 1/5] target-tricore: Added FTOUZ instruction
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 1/5] target-tricore: Added FTOUZ instruction |
Date: |
Wed, 11 Jan 2017 14:45:45 +0100 |
Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/tricore/fpu_helper.c | 27 +++++++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 3 +++
3 files changed, 31 insertions(+)
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 98fe9472b1..215c3970b1 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -215,3 +215,30 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
}
return (uint32_t)f_result;
}
+
+uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result;
+ int32_t flags;
+
+ result = float32_to_uint32_round_to_zero(f_arg, &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags & float_flag_invalid) {
+ flags &= ~float_flag_inexact;
+ if (float32_is_any_nan(f_arg)) {
+ result = 0;
+ }
+ } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
+ flags = float_flag_invalid;
+ result = 0;
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return result;
+}
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 9333e161ab..467c88013a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
+DEF_HELPER_2(ftouz, i32, env, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 36f734a662..eb6fdc3ca4 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6698,6 +6698,9 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RR_ITOF:
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
+ case OPC2_32_RR_FTOUZ:
+ gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.11.0
- [Qemu-devel] [PULL 0/5] tricore-patches, Bastian Koppelmann, 2017/01/11
- [Qemu-devel] [PULL 2/5] target-tricore: Added MADD.F and MSUB.F instructions, Bastian Koppelmann, 2017/01/11
- [Qemu-devel] [PULL 1/5] target-tricore: Added FTOUZ instruction,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 5/5] target-tricore: Add updfl instruction, Bastian Koppelmann, 2017/01/11
- [Qemu-devel] [PULL 3/5] target-tricore: Added new MOV instruction variant, Bastian Koppelmann, 2017/01/11
- [Qemu-devel] [PULL 4/5] target-tricore: Added new JNE instruction variant, Bastian Koppelmann, 2017/01/11
- Re: [Qemu-devel] [PULL 0/5] tricore-patches, Peter Maydell, 2017/01/12