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[Qemu-devel] [PULL 35/65] target-tricore: Use clz opcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 35/65] target-tricore: Use clz opcode |
Date: |
Tue, 10 Jan 2017 18:17:50 -0800 |
Tested-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/tricore/helper.h | 2 --
target/tricore/op_helper.c | 10 ----------
target/tricore/translate.c | 5 +++--
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 9333e16..2cf04e1 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -87,9 +87,7 @@ DEF_HELPER_FLAGS_2(min_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(ixmin, TCG_CALL_NO_RWG_SE, i64, i64, i32)
DEF_HELPER_FLAGS_2(ixmin_u, TCG_CALL_NO_RWG_SE, i64, i64, i32)
/* count leading ... */
-DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32)
-DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(cls, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index ac02e0a..3731d5e 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -1733,11 +1733,6 @@ EXTREMA_H_B(min, <)
#undef EXTREMA_H_B
-uint32_t helper_clo(target_ulong r1)
-{
- return clo32(r1);
-}
-
uint32_t helper_clo_h(target_ulong r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
@@ -1756,11 +1751,6 @@ uint32_t helper_clo_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
-uint32_t helper_clz(target_ulong r1)
-{
- return clz32(r1);
-}
-
uint32_t helper_clz_h(target_ulong r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 36f734a..69cdfb9 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6367,7 +6367,8 @@ static void decode_rr_logical_shift(CPUTriCoreState *env,
DisasContext *ctx)
tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_CLO:
- gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLO_H:
gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
@@ -6379,7 +6380,7 @@ static void decode_rr_logical_shift(CPUTriCoreState *env,
DisasContext *ctx)
gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLZ:
- gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLZ_H:
gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
--
2.9.3
- [Qemu-devel] [PULL 29/65] target-microblaze: Use clz opcode, (continued)
- [Qemu-devel] [PULL 29/65] target-microblaze: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 28/65] target-cris: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 24/65] tcg: Add clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 30/65] target-mips: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 31/65] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 34/65] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 33/65] target-s390x: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 36/65] target-unicore32: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 38/65] target-arm: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 32/65] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 35/65] target-tricore: Use clz opcode,
Richard Henderson <=
- [Qemu-devel] [PULL 37/65] target-xtensa: Use clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 39/65] target-i386: Use clz and ctz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 41/65] tcg/aarch64: Handle ctz and clz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 40/65] tcg/ppc: Handle ctz and clz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 42/65] tcg/arm: Handle ctz and clz opcodes, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 43/65] tcg/mips: Handle clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 44/65] tcg/s390: Handle clz opcode, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 47/65] tcg/i386: Allow bmi2 shiftx to have non-matching operands, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 45/65] tcg/i386: Fuly convert tcg_target_op_def, Richard Henderson, 2017/01/10
- [Qemu-devel] [PULL 46/65] tcg/i386: Hoist common arguments in tcg_out_op, Richard Henderson, 2017/01/10