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[Qemu-devel] [PATCH v2 04/11] aspeed/smc: autostrap CE0/1 configuration
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v2 04/11] aspeed/smc: autostrap CE0/1 configuration |
Date: |
Mon, 9 Jan 2017 17:24:40 +0100 |
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for
CE0 and CE1 and 4BYTE mode is autodetected for CE0.
On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are
strapped with register SCU70. We use the default settings from the
palmetto-bmc machine for now.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
---
hw/ssi/aspeed_smc.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
Changes since v1:
- splitted ast2400 from ast2500 strapping as they should be handled
in a different way. ast2400 strapping should be derived from SCU70
but it seems a little overly complex to do it now.
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9b31d5d27012..3bd381b13bc2 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -39,11 +39,14 @@
#define CONF_ENABLE_W2 18
#define CONF_ENABLE_W1 17
#define CONF_ENABLE_W0 16
-#define CONF_FLASH_TYPE4 9
-#define CONF_FLASH_TYPE3 7
-#define CONF_FLASH_TYPE2 5
-#define CONF_FLASH_TYPE1 3
-#define CONF_FLASH_TYPE0 1
+#define CONF_FLASH_TYPE4 8
+#define CONF_FLASH_TYPE3 6
+#define CONF_FLASH_TYPE2 4
+#define CONF_FLASH_TYPE1 2
+#define CONF_FLASH_TYPE0 0
+#define CONF_FLASH_TYPE_NOR 0x0
+#define CONF_FLASH_TYPE_NAND 0x1
+#define CONF_FLASH_TYPE_SPI 0x2
/* CE Control Register */
#define R_CE_CTRL (0x04 / 4)
@@ -436,6 +439,25 @@ static void aspeed_smc_reset(DeviceState *d)
s->regs[R_SEG_ADDR0 + i] =
aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
}
+
+ /* HW strapping for AST2500 FMC controllers */
+ if (s->ctrl->segments == aspeed_segments_ast2500_fmc) {
+ /* flash type is fixed to SPI for CE0 and CE1 */
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1);
+
+ /* 4BYTE mode is autodetected for CE0. Let's force it to 1 for
+ * now */
+ s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
+ }
+
+ /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
+ * configuration of the palmetto-bmc machine */
+ if (s->ctrl->segments == aspeed_segments_fmc) {
+ s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0);
+
+ s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0));
+ }
}
static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
--
2.7.4
- [Qemu-devel] [PATCH v2 00/11] Aspeed SMC controller fixes and improvements, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 01/11] aspeed/smc: remove call to reset in realize function, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 02/11] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 03/11] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 04/11] aspeed/smc: autostrap CE0/1 configuration,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v2 05/11] aspeed/smc: unfold the AspeedSMCController array, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 06/11] aspeed/smc: adjust the size of the register region, Cédric Le Goater, 2017/01/09
- [Qemu-devel] [PATCH v2 07/11] aspeed/smc: handle SPI flash Command mode, Cédric Le Goater, 2017/01/09
[Qemu-devel] [PATCH v2 08/11] aspeed/smc: reset flash after each test, Cédric Le Goater, 2017/01/09