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From: | mar.krzeminski |
Subject: | Re: [Qemu-devel] [PATCH v3] [i.MX] fix CS handling during SPI access. |
Date: | Fri, 6 Jan 2017 19:48:51 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 |
W dniu 06.01.2017 o 19:18, Jean-Christophe DUBOIS pisze:
Le 06/01/2017 à 13:28, mar.krzeminski a écrit :I saw that memset, my question is rather real HW also have 0s after reset (could be importantPlease make sure that in HW ECSPI_CONFIGREG_SS_POL bits are 0's after reset/power up (defaults).There is already a memset to 0 of all regs (including CONFIGREG) in the reset function.in some cases).Yes, all registers are set to 0 at reset except STATREG which is set to 3 (according to reference manual).
Thanks!
Thanks, Marcin
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