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[Qemu-devel] [PULL 25/25] target-arm: Add VBAR support to ARM1176 CPUs
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/25] target-arm: Add VBAR support to ARM1176 CPUs |
Date: |
Tue, 27 Dec 2016 15:21:17 +0000 |
From: Cédric Le Goater <address@hidden>
ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.
The VBAR feature is always set for ARMv7 because some legacy boards
require it even if this is not architecturally correct.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 1 +
target/arm/cpu.c | 9 +++++++++
target/arm/helper.c | 19 +++++++++++++------
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ca5c849..ab119e6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1125,6 +1125,7 @@ enum arm_features {
ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
ARM_FEATURE_PMU, /* has PMU support */
+ ARM_FEATURE_VBAR, /* has cp15 VBAR */
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 98e2c68..f5cb30a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -597,6 +597,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
} else {
set_feature(env, ARM_FEATURE_V6);
}
+
+ /* Always define VBAR for V7 CPUs even if it doesn't exist in
+ * non-EL3 configs. This is needed by some legacy boards.
+ */
+ set_feature(env, ARM_FEATURE_VBAR);
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
set_feature(env, ARM_FEATURE_V6);
@@ -721,6 +726,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
}
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ set_feature(env, ARM_FEATURE_VBAR);
+ }
+
register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b5b65ca..8dcabbf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1252,12 +1252,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.writefn = pmintenclr_write },
- { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .writefn = vbar_write,
- .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
- offsetof(CPUARMState, cp15.vbar_ns) },
- .resetvalue = 0 },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
@@ -5094,6 +5088,19 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
+ if (arm_feature(env, ARM_FEATURE_VBAR)) {
+ ARMCPRegInfo vbar_cp_reginfo[] = {
+ { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .writefn = vbar_write,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+ offsetof(CPUARMState, cp15.vbar_ns) },
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+ };
+ define_arm_cp_regs(cpu, vbar_cp_reginfo);
+ }
+
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
--
2.7.4
- [Qemu-devel] [PULL 15/25] aspeed: extend the board configuration with flash models, (continued)
- [Qemu-devel] [PULL 15/25] aspeed: extend the board configuration with flash models, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 16/25] aspeed: add support for the romulus-bmc board, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 17/25] aspeed: add a memory region for SRAM, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 18/25] aspeed: add the definitions for the AST2400 A1 SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 19/25] aspeed: change SoC revision of the palmetto-bmc machine, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 20/25] aspeed/scu: fix SCU region size, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 21/25] aspeed/smc: improve segment register support, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 22/25] aspeed/smc: set the number of flash modules for the FMC controller, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 23/25] hw/arm: remove trailing whitespace, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 24/25] hw/i2c: Add a NULL check for i2c slave init callbacks, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 25/25] target-arm: Add VBAR support to ARM1176 CPUs,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/12/27