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[Qemu-devel] [PATCH for-2.9 08/30] aspeed: add a memory region for SRAM
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH for-2.9 08/30] aspeed: add a memory region for SRAM |
Date: |
Tue, 29 Nov 2016 16:43:46 +0100 |
The size of the SRAM depends on the SoC model, so use a per-soc
definition when creating the region.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
---
hw/arm/aspeed_soc.c | 52 +++++++++++++++++++++++++++++++++++++--------
include/hw/arm/aspeed_soc.h | 2 ++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 82e27129a900..233a6b9bf59f 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -29,6 +29,7 @@
#define ASPEED_SOC_VIC_BASE 0x1E6C0000
#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
#define ASPEED_SOC_SCU_BASE 0x1E6E2000
+#define ASPEED_SOC_SRAM_BASE 0x1E720000
#define ASPEED_SOC_TIMER_BASE 0x1E782000
#define ASPEED_SOC_I2C_BASE 0x1E78A000
@@ -47,15 +48,37 @@ static const char *aspeed_soc_ast2500_typenames[] = {
"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
static const AspeedSoCInfo aspeed_socs[] = {
- { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
- 1, aspeed_soc_ast2400_spi_bases,
- "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
- { "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
- 1, aspeed_soc_ast2400_spi_bases,
- "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
- { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,
- 2, aspeed_soc_ast2500_spi_bases,
- "aspeed.smc.ast2500-fmc", aspeed_soc_ast2500_typenames },
+ {
+ .name = "ast2400-a0",
+ .cpu_model = "arm926",
+ .silicon_rev = AST2400_A0_SILICON_REV,
+ .sdram_base = AST2400_SDRAM_BASE,
+ .sram_size = 0x8000,
+ .spis_num = 1,
+ .spi_bases = aspeed_soc_ast2400_spi_bases,
+ .fmc_typename = "aspeed.smc.fmc",
+ .spi_typename = aspeed_soc_ast2400_typenames,
+ }, {
+ .name = "ast2400",
+ .cpu_model = "arm926",
+ .silicon_rev = AST2400_A0_SILICON_REV,
+ .sdram_base = AST2400_SDRAM_BASE,
+ .sram_size = 0x8000,
+ .spis_num = 1,
+ .spi_bases = aspeed_soc_ast2400_spi_bases,
+ .fmc_typename = "aspeed.smc.fmc",
+ .spi_typename = aspeed_soc_ast2400_typenames,
+ }, {
+ .name = "ast2500-a1",
+ .cpu_model = "arm1176",
+ .silicon_rev = AST2500_A1_SILICON_REV,
+ .sdram_base = AST2500_SDRAM_BASE,
+ .sram_size = 0x9000,
+ .spis_num = 2,
+ .spi_bases = aspeed_soc_ast2500_spi_bases,
+ .fmc_typename = "aspeed.smc.ast2500-fmc",
+ .spi_typename = aspeed_soc_ast2500_typenames,
+ },
};
/*
@@ -157,6 +180,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
return;
}
+ /* SRAM */
+ memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
+ sc->info->sram_size, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ vmstate_register_ram_global(&s->sram);
+ memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
+ &s->sram);
+
/* VIC */
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
if (err) {
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 6f1b679c97b1..1ab5deaa0813 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -29,6 +29,7 @@ typedef struct AspeedSoCState {
/*< public >*/
ARMCPU cpu;
MemoryRegion iomem;
+ MemoryRegion sram;
AspeedVICState vic;
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
@@ -46,6 +47,7 @@ typedef struct AspeedSoCInfo {
const char *cpu_model;
uint32_t silicon_rev;
hwaddr sdram_base;
+ uint64_t sram_size;
int spis_num;
const hwaddr *spi_bases;
const char *fmc_typename;
--
2.7.4
- [Qemu-devel] [PATCH for-2.9 00/30] Aspeed SoC fixes and model improvements, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 01/30] target-arm: Add VBAR support to ARM1176 CPUs, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 02/30] m25p80: add support for the mx66l1g45g, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 03/30] aspeed: QOMify the CPU object and attach it to the SoC, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 04/30] aspeed: remove cannot_destroy_with_object_finalize_yet, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 06/30] aspeed: extend the board configuration with flash models, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 05/30] aspeed: attach the second SPI controller object to the SoC, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 07/30] aspeed: add support for the romulus-bmc board, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 08/30] aspeed: add a memory region for SRAM,
Cédric Le Goater <=
- [Qemu-devel] [PATCH for-2.9 09/30] aspeed: add the definitions for the AST2400 A1 SoC, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 10/30] aspeed: change SoC revision of the palmetto-bmc machine, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 11/30] aspeed/scu: fix SCU region size, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 12/30] aspeed/smc: improve segment register support, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 13/30] aspeed/smc: set the number of flash modules for the FMC controller, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 14/30] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 15/30] aspeed/smc: introduce a aspeed_smc_flash_update_cs() helper, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 16/30] aspeed/smc: autostrap CE0/1 configuration, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 17/30] aspeed/smc: handle SPI flash Command mode, Cédric Le Goater, 2016/11/29
- [Qemu-devel] [PATCH for-2.9 18/30] aspeed/smc: extend tests for Command mode, Cédric Le Goater, 2016/11/29