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Re: [Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp |
Date: |
Tue, 22 Nov 2016 20:49:10 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Nikunj A Dadhania <address@hidden> writes:
> stxsd: Store VSX Scalar Dword
> stxssp: Store VSX Scalar SP
>
> Moreover, DQ-Form/DS-FORM instructions shares the same primary
> opcode(0x3D), bits 29:31 are used to decode the instruction. Us e a
> common routine to decode primary opcode(0x3D) - ds-form/dq-form
> instructions.
Realised that the below logic wast correct, should be something like this:
static void gen_dform3D(DisasContext *ctx)
{
if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
switch (ctx->opcode & 0x7) {
case 1: /* lxv */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxv(ctx);
}
break;
case 5: /* stxv */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxv(ctx);
}
break;
}
} else { /* DS-FORM */
switch (ctx->opcode & 0x3) {
case 0: /* lfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_stfdp(ctx);
}
break;
case 2: /* lxsd */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxsd(ctx);
}
break;
case 3: /* lxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxssp(ctx);
}
break;
}
}
return gen_invalid(ctx);
}
Will correct it in next revision.
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
> target-ppc/translate.c | 25 +++++++++++++++++++++++++
> target-ppc/translate/fp-ops.inc.c | 1 -
> target-ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++
> 3 files changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index f280851..bce607b 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6076,6 +6076,29 @@ static void gen_dform39(DisasContext *ctx)
> return gen_invalid(ctx);
> }
>
> +/* handles stfdp, stxsd, stxssp */
> +static void gen_dform3D(DisasContext *ctx)
> +{
> + switch (ctx->opcode & 0x7) {
> + case 0: /* lfdp */
> + if (ctx->insns_flags2 & PPC2_ISA205) {
> + return gen_stfdp(ctx);
> + }
> + break;
> + case 2: /* lxsd */
> + if (ctx->insns_flags2 & PPC2_ISA300) {
> + return gen_stxsd(ctx);
> + }
> + break;
> + case 3: /* lxssp */
> + if (ctx->insns_flags2 & PPC2_ISA300) {
> + return gen_stxssp(ctx);
> + }
> + break;
> + }
> + return gen_invalid(ctx);
> +}
> +
- [Qemu-devel] [PATCH ppc-for-2.9 0/9] POWER9 TCG enablements - part8, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 1/9] target-ppc: Consolidate instruction decode helpers, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 2/9] target-ppc: Fix xscmpodp and xscmpudp instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 3/9] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 9/9] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 7/9] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/22
- Re: [Qemu-devel] [PATCH 6/9] target-ppc: implement stxsd and stxssp,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH 8/9] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 5/9] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/22
- [Qemu-devel] [PATCH 4/9] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/22