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[Qemu-devel] [PATCH v6 02/10] ppc/xics: add a xics_get_cpu_index_by_pir
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v6 02/10] ppc/xics: add a xics_get_cpu_index_by_pir helper |
Date: |
Tue, 8 Nov 2016 09:08:02 +0100 |
We will need this helper to translate the server number of the XIVE
(which is a PIR) into an ICPState index number (which is a cpu index).
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v5:
- removed the dependency on XICS. The routine now uses a loop on all
CPUs of the machine like this is done in ppc_get_vcpu_by_dt_id()
hw/intc/xics.c | 11 +++++++++++
hw/ppc/ppc.c | 16 ++++++++++++++++
include/hw/ppc/xics.h | 1 +
target-ppc/cpu.h | 10 ++++++++++
4 files changed, 38 insertions(+)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index f24787e95013..cab8837245b3 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -49,6 +49,17 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
return -1;
}
+int xics_get_cpu_index_by_pir(int pir)
+{
+ PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
+
+ if (cpu) {
+ return cpu->parent_obj.cpu_index;
+ }
+
+ return -1;
+}
+
void xics_cpu_destroy(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 89458690097f..9386bda6f327 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1352,6 +1352,22 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
return NULL;
}
+PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
+{
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (env->spr_cb[SPR_PIR].default_value == pir) {
+ return cpu;
+ }
+ }
+
+ return NULL;
+}
+
void ppc_cpu_parse_features(const char *cpu_model)
{
CPUClass *cc;
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 1ee8663e9889..1dbcdf02b43c 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -196,6 +196,7 @@ void xics_set_nr_servers(XICSState *xics, uint32_t
nr_servers,
/* Internal XICS interfaces */
int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
+int xics_get_cpu_index_by_pir(int pir);
void icp_set_cppr(ICPState *icp, uint8_t cppr);
void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 1c90adb5d7b8..f05f73e1581f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2443,5 +2443,15 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
*/
PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
+/**
+ * ppc_get_vcpu_by_pir_id:
+ * @pir: Processor Identifier Register (SPR_PIR)
+ *
+ * Searches for a CPU by @pir.
+ *
+ * Returns: a PowerPCCPU struct
+ */
+PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
+
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
#endif /* PPC_CPU_H */
--
2.7.4
- [Qemu-devel] [PATCH v6 00/10] ppc/pnv: reworking the interrupt controller, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 01/10] ppc/xics: introduce a helper to insert a new ics, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 02/10] ppc/xics: add a xics_get_cpu_index_by_pir helper,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v6 03/10] ppc/xics: add a 'realize' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 04/10] ppc/xics: add a 'set_nr_servers' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 05/10] ppc/pnv: add a XICS object to the PowerNV machine, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 06/10] ppc/pnv: add MMIO regions for ICPs, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 07/10] ppc/pnv: link the CPUs to the machine XICS, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 08/10] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 09/10] ppc/pnv: Add OCC model stub with interrupt support, Cédric Le Goater, 2016/11/08
- [Qemu-devel] [PATCH v6 10/10] ppc/pnv: Add Naples chip support for LPC interrupts, Cédric Le Goater, 2016/11/08