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[Qemu-devel] [PATCH v1 25/30] target-sparc: implement UA2005 ASI_MMU (0x
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) |
Date: |
Fri, 4 Nov 2016 21:50:26 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target-sparc/ldst_helper.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 57b3b97..d34795a 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1394,6 +1394,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr,
ret = env->scratch[i];
break;
}
+ case ASI_MMU: /* UA2005 Context ID registers */
+ switch ((addr >> 3) & 0x3) {
+ case 1:
+ ret = env->dmmu.mmu_primary_context;
+ break;
+ case 2:
+ ret = env->dmmu.mmu_secondary_context;
+ break;
+ default:
+ cpu_unassigned_access(cs, addr, true, false, 1, size);
+ }
+ break;
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
@@ -1712,6 +1724,25 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
addr, target_ulong val,
env->scratch[i] = val;
return;
}
+ case ASI_MMU: /* UA2005 Context ID registers */
+ {
+ switch ((addr >> 3) & 0x3) {
+ case 1:
+ env->dmmu.mmu_primary_context = val;
+ env->immu.mmu_primary_context = val;
+ tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_IDX, MMU_KERNEL_IDX, -1);
+ break;
+ case 2:
+ env->dmmu.mmu_secondary_context = val;
+ env->immu.mmu_secondary_context = val;
+ tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_SECONDARY_IDX,
+ MMU_KERNEL_SECONDARY_IDX, -1);
+ break;
+ default:
+ cpu_unassigned_access(cs, addr, true, false, 1, size);
+ }
+ }
+ return;
case ASI_QUEUE: /* UA2005 CPU mondo queue */
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
--
1.8.3.1
- [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register, (continued)
- [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 25/30] target-sparc: implement UA2005 ASI_MMU (0x21),
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 28/30] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 29/30] target-sparc: move common cpu initialisation routines to sparc64.c, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2016/11/04