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[Qemu-devel] [PATCH 13/23] target-m68k: update move to/from ccr/sr
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 13/23] target-m68k: update move to/from ccr/sr |
Date: |
Tue, 25 Oct 2016 16:50:11 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 53 ++++++++++++++++++++-----------------------------
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 681f3a8..37faefe 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1368,12 +1368,10 @@ static TCGv gen_get_ccr(DisasContext *s)
DISAS_INSN(move_from_ccr)
{
- TCGv reg;
TCGv ccr;
ccr = gen_get_ccr(s);
- reg = DREG(insn, 0);
- gen_partset_reg(OS_WORD, reg, ccr);
+ DEST_EA(env, insn, OS_WORD, ccr, NULL);
}
DISAS_INSN(neg)
@@ -1400,37 +1398,31 @@ static void gen_set_sr_im(DisasContext *s, uint16_t
val, int ccr_only)
}
}
-static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
- int ccr_only)
+static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{
TCGv tmp;
- TCGv reg;
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i32(QREG_CC_DEST, val, 0xf);
+ tcg_gen_shri_i32(tmp, val, 4);
+ tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
+ if (!ccr_only) {
+ gen_helper_set_sr(cpu_env, val);
+ }
+}
+static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
+ int ccr_only)
+{
+ TCGv src;
s->cc_op = CC_OP_FLAGS;
- if ((insn & 0x38) == 0)
- {
- tmp = tcg_temp_new();
- reg = DREG(insn, 0);
- tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
- tcg_gen_shri_i32(tmp, reg, 4);
- tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
- if (!ccr_only) {
- gen_helper_set_sr(cpu_env, reg);
- }
- }
- else if ((insn & 0x3f) == 0x3c)
- {
- uint16_t val;
- val = read_im16(env, s);
- gen_set_sr_im(s, val, ccr_only);
- }
- else
- disas_undef(env, s, insn);
+ SRC_EA(env, src, OS_WORD, 0, NULL);
+ gen_set_sr(s, src, ccr_only);
}
+
DISAS_INSN(move_to_ccr)
{
- gen_set_sr(env, s, insn, 1);
+ gen_move_to_sr(env, s, insn, 1);
}
DISAS_INSN(not)
@@ -1957,16 +1949,14 @@ DISAS_INSN(strldsr)
DISAS_INSN(move_from_sr)
{
- TCGv reg;
TCGv sr;
- if (IS_USER(s)) {
+ if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
sr = gen_get_sr(s);
- reg = DREG(insn, 0);
- gen_partset_reg(OS_WORD, reg, sr);
+ DEST_EA(env, insn, OS_WORD, sr, NULL);
}
DISAS_INSN(move_to_sr)
@@ -1975,7 +1965,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
- gen_set_sr(env, s, insn, 0);
+ gen_move_to_sr(env, s, insn, 0);
gen_lookup_tb(s);
}
@@ -2872,6 +2862,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(clr, 4200, ff00);
BASE(undef, 42c0, ffc0);
INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
+ INSN(move_from_ccr, 42c0, ffc0, M68000);
INSN(neg, 4480, fff8, CF_ISA_A);
INSN(neg, 4400, ff00, M68000);
INSN(undef, 44c0, ffc0, M68000);
--
2.7.4
- [Qemu-devel] [PATCH 04/23] target-m68k: manage scaled index, (continued)
- [Qemu-devel] [PATCH 04/23] target-m68k: manage scaled index, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 06/23] target-m68k: set disassembler mode to 680x0 or coldfire, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 03/23] target-m68k: define m680x0 CPUs and features, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 09/23] target-m68k: REG() macro cleanup, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 07/23] target-m68k: define operand sizes, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 05/23] target-m68k: introduce read_imXX() functions, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 12/23] target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit(), Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 18/23] target-m68k: Remove incorrect clearing of cc_x, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 16/23] target-m68k: Print flags properly, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 17/23] target-m68k: Some fixes to SR and flags management, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 13/23] target-m68k: update move to/from ccr/sr,
Laurent Vivier <=
- [Qemu-devel] [PATCH 15/23] target-m68k: update CPU flags management, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 14/23] target-m68k: don't update cc_dest in helpers, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 21/23] target-m68k: Use setcond for scc, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 20/23] target-m68k: Introduce DisasCompare, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 19/23] target-m68k: Reorg flags handling, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 11/23] target-m68k: Replace helper_xflag_lt with setcond, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 22/23] target-m68k: Optimize some comparisons, Laurent Vivier, 2016/10/25
- [Qemu-devel] [PATCH 23/23] target-m68k: Optimize gen_flush_flags, Laurent Vivier, 2016/10/25
- Re: [Qemu-devel] [PATCH 00/23] target-m68k: prepare to introduce 680x0 instruction set, Richard Henderson, 2016/10/25