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[Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1) |
Date: |
Mon, 17 Oct 2016 19:40:30 +0100 |
From: Thomas Huth <address@hidden>
The M1 and M2 bits are both used for configuring the endianness
of the AHB master interfaces, so the second PL080_CONF_M1 should
be PL080_CONF_M2 instead.
Buglink: https://bugs.launchpad.net/qemu/+bug/1631773
Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/dma/pl080.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
index 3bed5c3..7724c93 100644
--- a/hw/dma/pl080.c
+++ b/hw/dma/pl080.c
@@ -351,7 +351,7 @@ static void pl080_write(void *opaque, hwaddr offset,
break;
case 12: /* Configuration */
s->conf = value;
- if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
+ if (s->conf & (PL080_CONF_M1 | PL080_CONF_M2)) {
qemu_log_mask(LOG_UNIMP,
"pl080_write: Big-endian DMA not implemented\n");
}
--
2.7.4
- [Qemu-devel] [PULL 20/25] target-arm: Comments added to identify cases in a switch, (continued)
- [Qemu-devel] [PULL 20/25] target-arm: Comments added to identify cases in a switch, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 05/25] aspeed: move the flash module mapping address under the controller definition, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 04/25] aspeed: rename the smc object to fmc, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 24/25] hw/intc/arm_gicv3: Fix ICC register tracepoints, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 02/25] Reducing stack frame size in stream_process_mem2s(), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 14/25] hw/arm/virt: no ITS on older machine types, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 15/25] tests: add a m25p80 test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 21/25] Fix masking of PC lower bits when doing exception returns, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrite of tag field on PC load, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 01/25] docs/generic-loader: Update the document, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1),
Peter Maydell <=
- [Qemu-devel] [PULL 17/25] pxa2xx: Auto-assign name for i2c bus in i2c_init_bus., Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 16/25] tests: cleanup ptimer-test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 03/25] target-arm: kvm: use AddressSpace-specific listener, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 09/25] aspeed: add support for the SMC segment registers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 18/25] target-arm: Infrastucture changes to enable handling of tagged address loading into PC, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 23/25] target-arm: Add trace events for the generic timers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 25/25] hw/char/pl011: Add trace events, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 06/25] aspeed: extend the number of host SPI controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 22/25] target-arm: Implement dummy MDCCINT_EL1, Peter Maydell, 2016/10/17