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Re: [Qemu-devel] [PATCH v5 06/35] tcg: Add EXCP_ATOMIC
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v5 06/35] tcg: Add EXCP_ATOMIC |
Date: |
Mon, 10 Oct 2016 17:17:16 +0100 |
User-agent: |
mu4e 0.9.17; emacs 25.1.50.3 |
Richard Henderson <address@hidden> writes:
> When we cannot emulate an atomic operation within a parallel
> context, this exception allows us to stop the world and try
> again in a serial context.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> cpu-exec-common.c | 6 ++++++
> cpu-exec.c | 30 ++++++++++++++++++++++++++++++
> cpus.c | 2 ++
> include/exec/cpu-all.h | 1 +
> include/exec/exec-all.h | 1 +
> include/qemu-common.h | 1 +
> linux-user/main.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
> tcg/tcg.h | 1 +
> translate-all.c | 1 +
> 9 files changed, 88 insertions(+)
>
> diff --git a/cpu-exec-common.c b/cpu-exec-common.c
> index 0cb4ae6..767d9c6 100644
> --- a/cpu-exec-common.c
> +++ b/cpu-exec-common.c
> @@ -77,3 +77,9 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
> }
> siglongjmp(cpu->jmp_env, 1);
> }
> +
> +void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc)
> +{
> + cpu->exception_index = EXCP_ATOMIC;
> + cpu_loop_exit_restore(cpu, pc);
> +}
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 8823d23..d7ccc7f 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -222,6 +222,36 @@ static void cpu_exec_nocache(CPUState *cpu, int
> max_cycles,
> }
> #endif
>
> +static void cpu_exec_step(CPUState *cpu)
> +{
> + CPUArchState *env = (CPUArchState *)cpu->env_ptr;
> + TranslationBlock *tb;
> + target_ulong cs_base, pc;
> + uint32_t flags;
> +
> + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
> + tb = tb_gen_code(cpu, pc, cs_base, flags,
> + 1 | CF_NOCACHE | CF_IGNORE_ICOUNT);
> + tb->orig_tb = NULL;
> + /* execute the generated code */
> + trace_exec_tb_nocache(tb, pc);
> + cpu_tb_exec(cpu, tb);
> + tb_phys_invalidate(tb, -1);
> + tb_free(tb);
> +}
Hmm it is a shame we can't share more code with cpu_exec_nocache here
because we are just essentially saying run an uncached single
instruction translation. In fact the c&p'ed trace statement reveals its
origin ;-)
> +
> +void cpu_exec_step_atomic(CPUState *cpu)
> +{
> + start_exclusive();
> +
> + /* Since we got here, we know that parallel_cpus must be true. */
> + parallel_cpus = false;
> + cpu_exec_step(cpu);
> + parallel_cpus = true;
> +
> + end_exclusive();
> +}
> +
> struct tb_desc {
> target_ulong pc;
> target_ulong cs_base;
> diff --git a/cpus.c b/cpus.c
> index 31204bb..cfd5cdc 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -1497,6 +1497,8 @@ static void tcg_exec_all(void)
> if (r == EXCP_DEBUG) {
> cpu_handle_guest_debug(cpu);
> break;
> + } else if (r == EXCP_ATOMIC) {
> + cpu_exec_step_atomic(cpu);
> }
> } else if (cpu->stop || cpu->stopped) {
> if (cpu->unplug) {
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index b6a7059..1f7e9d8 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -31,6 +31,7 @@
> #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or
> singlestep */
> #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external
> event) */
> #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
> +#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
>
> /* some important defines:
> *
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 336a57c..13633a2 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -60,6 +60,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
> void cpu_exec_init(CPUState *cpu, Error **errp);
> void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
> void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
> +void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
>
> #if !defined(CONFIG_USER_ONLY)
> void cpu_reloading_memory_map(void);
> diff --git a/include/qemu-common.h b/include/qemu-common.h
> index 9e8b0bd..291f98d 100644
> --- a/include/qemu-common.h
> +++ b/include/qemu-common.h
> @@ -80,6 +80,7 @@ void tcg_exec_init(unsigned long tb_size);
> bool tcg_enabled(void);
>
> void cpu_exec_init_all(void);
> +void cpu_exec_step_atomic(CPUState *cpu);
>
> /**
> * Sends a (part of) iovec down a socket, yielding when the socket is full,
> or
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 9e4b430..ae68672 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -354,6 +354,9 @@ void cpu_loop(CPUX86State *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> pc = env->segs[R_CS].base + env->eip;
> EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x -
> aborting\n",
> @@ -848,6 +851,9 @@ void cpu_loop(CPUARMState *env)
> case EXCP_YIELD:
> /* nothing to do here for user-mode, just resume guest code */
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> error:
> EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> @@ -1048,6 +1054,9 @@ void cpu_loop(CPUARMState *env)
> case EXCP_YIELD:
> /* nothing to do here for user-mode, just resume guest code */
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> abort();
> @@ -1139,6 +1148,9 @@ void cpu_loop(CPUUniCore32State *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> goto error;
> }
> @@ -1412,6 +1424,9 @@ void cpu_loop (CPUSPARCState *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> printf ("Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -1951,6 +1966,9 @@ void cpu_loop(CPUPPCState *env)
> case EXCP_INTERRUPT:
> /* just indicate that signals should be handled asap */
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
> break;
> @@ -2626,6 +2644,9 @@ done_syscall:
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> error:
> EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> @@ -2713,6 +2734,9 @@ void cpu_loop(CPUOpenRISCState *env)
> case EXCP_NR:
> qemu_log_mask(CPU_LOG_INT, "\nNR\n");
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x -
> aborting\n",
> trapnr);
> @@ -2789,6 +2813,9 @@ void cpu_loop(CPUSH4State *env)
> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> break;
>
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> printf ("Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -2856,6 +2883,9 @@ void cpu_loop(CPUCRISState *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> printf ("Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -2972,6 +3002,9 @@ void cpu_loop(CPUMBState *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> printf ("Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -3075,6 +3108,9 @@ void cpu_loop(CPUM68KState *env)
> }
> }
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x -
> aborting\n", trapnr);
> abort();
> @@ -3311,6 +3347,9 @@ void cpu_loop(CPUAlphaState *env)
> case EXCP_INTERRUPT:
> /* Just indicate that signals should be handled asap. */
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> printf ("Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -3440,6 +3479,9 @@ void cpu_loop(CPUS390XState *env)
> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> break;
>
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
> default:
> fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
> cpu_dump_state(cs, stderr, fprintf, 0);
> @@ -3694,6 +3736,9 @@ void cpu_loop(CPUTLGState *env)
> case TILEGX_EXCP_REG_UDN_ACCESS:
> gen_sigill_reg(env);
> break;
> + case EXCP_ATOMIC:
> + cpu_exec_step_atomic(cs);
> + break;
This just makes me sad about the re-factoring needed for main, but not a
problem for this patch set to solve ;-)
> default:
> fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
> g_assert_not_reached();
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index c9949aa..3b21156 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -704,6 +704,7 @@ struct TCGContext {
> };
>
> extern TCGContext tcg_ctx;
> +extern bool parallel_cpus;
>
> static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
> {
> diff --git a/translate-all.c b/translate-all.c
> index 8ca393c..4200869 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -119,6 +119,7 @@ static void *l1_map[V_L1_SIZE];
>
> /* code generation context */
> TCGContext tcg_ctx;
> +bool parallel_cpus;
>
> /* translation block context */
> #ifdef CONFIG_USER_ONLY
However:
Reviewed-by: Alex Bennée <address@hidden>
--
Alex Bennée
- [Qemu-devel] [PATCH v5 29/35] target-arm: emulate SWP with atomic_xchg helper, (continued)
- [Qemu-devel] [PATCH v5 29/35] target-arm: emulate SWP with atomic_xchg helper, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 31/35] linux-user: remove handling of ARM's EXCP_STREX, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 32/35] linux-user: remove handling of aarch64's EXCP_STREX, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 28/35] target-arm: emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 30/35] target-arm: emulate aarch64's LL/SC using cmpxchg helpers, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 34/35] target-alpha: Introduce MMU_PHYS_IDX, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 33/35] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 35/35] target-alpha: Emulate LL/SC using cmpxchg helpers, Richard Henderson, 2016/10/09
- [Qemu-devel] [PATCH v5 06/35][RESEND] tcg: Add EXCP_ATOMIC, Richard Henderson, 2016/10/10
- Message not available
- Re: [Qemu-devel] [PATCH v5 06/35] tcg: Add EXCP_ATOMIC,
Alex Bennée <=