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[Qemu-devel] [PULL 09/29] target-ppc: improve lxvw4x implementation
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 09/29] target-ppc: improve lxvw4x implementation |
Date: |
Thu, 6 Oct 2016 23:02:55 +1100 |
From: Nikunj A Dadhania <address@hidden>
Load 8byte at a time and manipulate.
Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+
Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+
Vector load results in (32-bit elements):
+----------+----------+----------+----------+
| 00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[dwg: Slight tweak to commit description]
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate/vsx-impl.inc.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index c4c50dd..ec871b2 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -75,7 +75,6 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_lxvw4x(DisasContext *ctx)
{
TCGv EA;
- TCGv_i64 tmp;
TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
if (unlikely(!ctx->vsx_enabled)) {
@@ -84,22 +83,27 @@ static void gen_lxvw4x(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
- tmp = tcg_temp_new_i64();
gen_addr_reg_index(ctx, EA);
- gen_qemu_ld32u_i64(ctx, tmp, EA);
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_ld32u_i64(ctx, xth, EA);
- tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
-
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_ld32u_i64(ctx, tmp, EA);
- tcg_gen_addi_tl(EA, EA, 4);
- gen_qemu_ld32u_i64(ctx, xtl, EA);
- tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
-
+ if (ctx->le_mode) {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_shri_i64(t1, t0, 32);
+ tcg_gen_deposit_i64(xth, t1, t0, 32, 32);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEQ);
+ tcg_gen_shri_i64(t1, t0, 32);
+ tcg_gen_deposit_i64(xtl, t1, t0, 32, 32);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ } else {
+ tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
+ tcg_gen_addi_tl(EA, EA, 8);
+ tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
+ }
tcg_temp_free(EA);
- tcg_temp_free_i64(tmp);
}
#define VSX_STORE_SCALAR(name, operation) \
--
2.7.4
- [Qemu-devel] [PULL 00/29] ppc-for-2.8 queue 20161006, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 02/29] tests: Test IPv6 and ppc64 in the PXE tester, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 07/29] target-ppc: Implement mfvsrld instruction, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 20/29] target-ppc/kvm: Add a wrapper function to check for KVM-PR, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 04/29] hw/ppc/spapr: Move code related to "ibm, pa-features" to a separate function, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 14/29] target-ppc: add stxvb16x instruction, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 09/29] target-ppc: improve lxvw4x implementation,
David Gibson <=
- [Qemu-devel] [PULL 16/29] target-ppc: add vector compare not equal instructions, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 08/29] target-ppc: Implement mtvsrdd instruction, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 15/29] target-ppc: fix invalid mask - cmpl, bctar, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 03/29] pseries: Add 2.8 machine type, set up compatibility macros, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 26/29] tests: enable ohci/uhci/xhci tests on PPC64, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 17/29] target-ppc: add vclzlsbb/vctzlsbb instructions, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 21/29] target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 27/29] spapr: fix check of cpu alias name in spapr_get_cpu_core_type(), David Gibson, 2016/10/06
- [Qemu-devel] [PULL 22/29] target-ppc: fix vmx instruction type/type2, David Gibson, 2016/10/06
- [Qemu-devel] [PULL 05/29] hw/ppc/spapr: Fix the selection of the processor features, David Gibson, 2016/10/06