[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instructio
|
From: |
Richard Henderson |
|
Subject: |
Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction |
|
Date: |
Wed, 28 Sep 2016 13:21:00 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 |
On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
> + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
Why are you using t0?
r~
[Qemu-devel] [PATCH v5 5/9] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/28
[Qemu-devel] [PATCH v5 4/9] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/09/28
[Qemu-devel] [PATCH v5 2/9] target-ppc: Implement mtvsrdd instruction, Nikunj A Dadhania, 2016/09/28
[Qemu-devel] [PATCH v5 7/9] target-ppc: add stxvh8x instruction, Nikunj A Dadhania, 2016/09/28
[Qemu-devel] [PATCH v5 1/9] target-ppc: Implement mfvsrld instruction, Nikunj A Dadhania, 2016/09/28