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Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation s
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) |
Date: |
Mon, 26 Sep 2016 18:24:43 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
On 26/09/2016 18:20, Andreas Färber wrote:
> Am 26.09.2016 um 18:17 schrieb Richard Henderson:
>> On 09/26/2016 05:20 AM, Paolo Bonzini wrote:
>>> On 26/09/2016 12:56, Sagar Karandikar wrote:
>>>> -cpu-qom.h merged into cpu.h
>>>
>>> Please follow the model of other targets. RISCVCPUClass and the
>>> RISCVCPU typedef should be in cpu-qom.h.
>>
>> I thought we had this discussion before, and cpu-qom.h is sort of a
>> legacy header, and that new targets shouldn't use it.
>
> Yes, a concept that didn't quite work out, sadly. Just cpu.h is fine.
Hmm, maybe since 2.7.0 it started working out better? :)
The point of cpu-qom.h is to allow using the RISCVCPU symbol in target-
specific header files, without forcing all files including said header
to be compiled per-target. See for example
commit 4da6f8d954429c0cd1471d25cb9dbe909607374e
Author: Paolo Bonzini <address@hidden>
Date: Tue Mar 15 13:49:25 2016 +0100
target-i386: make cpu-qom.h not target specific
Make X86CPU an opaque type within cpu-qom.h, and move all definitions of
private methods, as well as all type definitions that require knowledge
of the layout to cpu.h. This helps making files independent of NEED_CPU_H
if they only need to pass around CPU pointers.
Signed-off-by: Paolo Bonzini <address@hidden>
You cannot include the definition of struct FooCPU in cpu-qom.h, because
it embeds "CPUFooState env;" and CPUFooState uses target_long. Still it's
a nice improvement, for example it's now possible to compile device models
common to arm-softmmu and aarch64-softmmu (or sh4/sh4eb, etc.) just once.
Paolo
- [Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions, (continued)
- [Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Paolo Bonzini, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Richard Henderson, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Andreas Färber, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G),
Paolo Bonzini <=
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Andreas Färber, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Paolo Bonzini, 2016/09/26