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Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/s


From: Alex Bennée
Subject: Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation
Date: Mon, 12 Sep 2016 09:39:35 +0100
User-agent: mu4e 0.9.17; emacs 25.1.12

David Gibson <address@hidden> writes:

> On Wed, Sep 07, 2016 at 08:13:31AM +0100, Alex Bennée wrote:
>>
>> David Gibson <address@hidden> writes:
>>
>> > On Wed, Sep 07, 2016 at 10:17:42AM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson <address@hidden> writes:
>> >>
>> >> > [ Unknown signature status ]
>> >> > On Fri, Sep 02, 2016 at 12:02:55PM +0530, Nikunj A Dadhania wrote:
>> >> >> Signed-off-by: Nikunj A Dadhania <address@hidden>
>> >> >
>> >> > This really needs a comment indicating that this implementation isn't
>> >> > strictly correct (although probably good enough in practice).
>> >>
>> >> Sure. And it also does not help if someone uses any store other than
>> >> store conditional, that isn't taken care.
>> >>
>> >> Assumption here is the locking primitives use load with reservation and
>> >> store conditional. And no other ld/st variant touch this memory.
>> >
>> > So, a) I don't think this really relies on that: an ordinary store
>> > (assuming it changes the value) will still get picked up the cmpxchg.
>> > Well.. at least after a suitable memory barrier.  Matching memory
>> > models between emulated and host cpus is a whole other kettle of fish.
>>
>> Have you seen Pranith's memory barrier patches?
>
> I have not.

They are now in Richard's tcg-next queue

Message-Id: <address@hidden>
Subject: [Qemu-devel] [PULL 00/18] tcg queued patches

All the backends support the new fence op, so far only ARM, Alpha and
x86 emit the fence TCGOps as these are best added by someone who
understands the frontend well.

>> >
>> > I think this does matter, IIRC a kernel spin unlock on ppc is a
>> > barrier + plain store, no load locked or store conditional.
>> >
>> >> > Specifically a racing store which happens to store the same value
>> >> > which was already in memory should clobber the reservation, but won't
>> >> > with this implementation.
>> >> >
>> >> > I had a long discussion at KVM Forum with Emilio Costa about this, in
>> >> > which I discovered just how hard it is to strictly implement
>> >> > store-conditional semantics in terms of anything else.  So, this is
>> >> > probably a reasonable substitute, but we should note the fact that
>> >> > it's not 100%.
>> >>
>> >> I will update the commit log.
>> >>
>> >> Regards,
>> >> Nikunj
>> >>
>>
>>


--
Alex Bennée



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