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[Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction |
Date: |
Thu, 28 Jul 2016 23:44:18 +0530 |
extswsli : Extend Sign Word & Shift Left Immediate
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 82349ed..fc3d371 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2328,6 +2328,30 @@ static void gen_sradi1(DisasContext *ctx)
gen_sradi(ctx, 1);
}
+/* extswsli & extswsli. */
+static inline void gen_extswsli(DisasContext *ctx, int n)
+{
+ int sh = SH(ctx->opcode) + (n << 5);
+ TCGv dst = cpu_gpr[rA(ctx->opcode)];
+ TCGv src = cpu_gpr[rS(ctx->opcode)];
+
+ tcg_gen_ext32s_tl(dst, src);
+ tcg_gen_shli_tl(dst, dst, sh);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, dst);
+ }
+}
+
+static void gen_extswsli0(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 0);
+}
+
+static void gen_extswsli1(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 1);
+}
+
/* srd & srd. */
static void gen_srd(DisasContext *ctx)
{
@@ -6227,6 +6251,10 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
+GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
+GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
#endif
#if defined(TARGET_PPC64)
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
--
2.7.4
- [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 1/8] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 2/8] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 3/8] target-ppc: add dtstsfi[q] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 4/8] target-ppc: add vabsdu[b, h, w] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 6/8] target-ppc: add vslv instruction, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction, Nikunj A Dadhania, 2016/07/28
- Re: [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2, David Gibson, 2016/07/29