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[Qemu-devel] [PULL v4 16/57] acpi: add DMAR scope definition for root IO
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v4 16/57] acpi: add DMAR scope definition for root IOAPIC |
Date: |
Thu, 21 Jul 2016 19:27:20 +0300 |
From: Peter Xu <address@hidden>
To enable interrupt remapping for intel IOMMU device, each IOAPIC device
in the system reported via ACPI MADT must be explicitly enumerated under
one specific remapping hardware unit. This patch adds the root-complex
IOAPIC into the default DMAR device.
Please refer to VT-d spec 8.3.1.1 for more information.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
include/hw/acpi/acpi-defs.h | 13 +++++++++++++
include/hw/pci-host/q35.h | 8 ++++++++
hw/i386/acpi-build.c | 20 +++++++++++++++++---
3 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index ea9be0b..41c1d95 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -571,6 +571,18 @@ enum {
/*
* Sub-structures for DMAR
*/
+
+/* Device scope structure for DRHD. */
+struct AcpiDmarDeviceScope {
+ uint8_t entry_type;
+ uint8_t length;
+ uint16_t reserved;
+ uint8_t enumeration_id;
+ uint8_t bus;
+ uint16_t path[0]; /* list of dev:func pairs */
+} QEMU_PACKED;
+typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
+
/* Type 0: Hardware Unit Definition */
struct AcpiDmarHardwareUnit {
uint16_t type;
@@ -579,6 +591,7 @@ struct AcpiDmarHardwareUnit {
uint8_t reserved;
uint16_t pci_segment; /* The PCI Segment associated with this unit */
uint64_t address; /* Base address of remapping hardware register-set */
+ AcpiDmarDeviceScope scope[0];
} QEMU_PACKED;
typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 0d64032..94486fd 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -179,4 +179,12 @@ typedef struct Q35PCIHost {
uint64_t mch_mcfg_base(void);
+/*
+ * Arbitary but unique BNF number for IOAPIC device.
+ *
+ * TODO: make sure there would have no conflict with real PCI bus
+ */
+#define Q35_PSEUDO_BUS_PLATFORM (0xff)
+#define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
+
#endif /* HW_Q35_H */
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 06682f1..77c40d9 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -81,6 +81,9 @@
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
+/* Default IOAPIC ID */
+#define ACPI_BUILD_IOAPIC_ID 0x0
+
typedef struct AcpiMcfgInfo {
uint64_t mcfg_base;
uint32_t mcfg_size;
@@ -384,7 +387,6 @@ build_madt(GArray *table_data, BIOSLinker *linker,
PCMachineState *pcms)
io_apic = acpi_data_push(table_data, sizeof *io_apic);
io_apic->type = ACPI_APIC_IO;
io_apic->length = sizeof(*io_apic);
-#define ACPI_BUILD_IOAPIC_ID 0x0
io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
io_apic->interrupt = cpu_to_le32(0);
@@ -2468,6 +2470,9 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
AcpiDmarHardwareUnit *drhd;
uint8_t dmar_flags = 0;
X86IOMMUState *iommu = x86_iommu_get_default();
+ AcpiDmarDeviceScope *scope = NULL;
+ /* Root complex IOAPIC use one path[0] only */
+ size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
assert(iommu);
if (iommu->intr_supported) {
@@ -2479,13 +2484,22 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
dmar->flags = dmar_flags;
/* DMAR Remapping Hardware Unit Definition structure */
- drhd = acpi_data_push(table_data, sizeof(*drhd));
+ drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
- drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
+ drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
drhd->pci_segment = cpu_to_le16(0);
drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
+ /* Scope definition for the root-complex IOAPIC. See VT-d spec
+ * 8.3.1 (version Oct. 2014 or later). */
+ scope = &drhd->scope[0];
+ scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
+ scope->length = ioapic_scope_size;
+ scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
+ scope->bus = Q35_PSEUDO_BUS_PLATFORM;
+ scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC);
+
build_header(linker, table_data, (void *)(table_data->data + dmar_start),
"DMAR", table_data->len - dmar_start, 1, NULL, NULL);
}
--
MST
- [Qemu-devel] [PULL v4 06/57] hw/grackle: fix PCI bus initialization, (continued)
- [Qemu-devel] [PULL v4 06/57] hw/grackle: fix PCI bus initialization, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 07/57] hw/prep: realize the PCI root bus as part of the prep init, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 08/57] hw/versatile: realize the PCI root bus as part of the versatile init, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 09/57] x86-iommu: introduce parent class, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 10/57] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 11/57] x86-iommu: provide x86_iommu_get_default, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 12/57] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 13/57] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 14/57] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 15/57] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 16/57] acpi: add DMAR scope definition for root IOAPIC,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v4 17/57] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 18/57] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 19/57] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 20/57] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 22/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 23/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 24/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 25/57] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v4 26/57] ioapic: register IOMMU IEC notifier for ioapic, Michael S. Tsirkin, 2016/07/21