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[Qemu-devel] [PULL 03/28] target-i386: Mask mtrr mask based on CPU physi
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 03/28] target-i386: Mask mtrr mask based on CPU physical address limits |
Date: |
Tue, 19 Jul 2016 14:22:31 -0300 |
From: "Dr. David Alan Gilbert" <address@hidden>
The CPU GPs if we try and set a bit in a variable MTRR mask above
the limit of physical address bits on the host. We hit this
when loading a migration from a host with a larger physical
address limit than our destination (e.g. a Xeon->i7 of same
generation) but previously used to get away with it
until 48e1a45 started checking that msr writes actually worked.
It seems in our case the GP probably comes from KVM emulating
that GP.
Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target-i386/kvm.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 9327523..2f1cc62 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1716,6 +1716,8 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
}
if (has_msr_mtrr) {
+ uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
+
kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
@@ -1729,10 +1731,15 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
+ /* The CPU GPs if we write to a bit above the physical limit of
+ * the host CPU (and KVM emulates that)
+ */
+ uint64_t mask = env->mtrr_var[i].mask;
+ mask &= phys_mask;
+
kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
env->mtrr_var[i].base);
- kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
- env->mtrr_var[i].mask);
+ kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
}
}
--
2.5.5
- [Qemu-devel] [PULL 00/28] x86 queue for -rc0, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 01/28] target-i386: Provide TCG_PHYS_ADDR_BITS, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 02/28] target-i386: Allow physical address bits to be set, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 03/28] target-i386: Mask mtrr mask based on CPU physical address limits,
Eduardo Habkost <=
- [Qemu-devel] [PULL 05/28] target-i386: Use uint32_t for X86CPU.apic_id, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 04/28] target-i386: Fill high bits of mtrr mask, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 06/28] pc: Add x86_topo_ids_from_apicid(), Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 07/28] target-i386: Set physical address bits based on host, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 09/28] pc: cpu: Consolidate apic-id validity checks in pc_cpu_pre_plug(), Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 08/28] pc: Extract CPU lookup into a separate function, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 10/28] target-i386: Replace custom apic-id setter/getter with static property, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 11/28] target-i386: Add socket/core/thread properties to X86CPU, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 12/28] target-i386: Add support for UMIP and RDPID CPUID bits, Eduardo Habkost, 2016/07/19
- [Qemu-devel] [PULL 13/28] target-i386: cpu: Do not ignore error and fix apic parent, Eduardo Habkost, 2016/07/19