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Re: [Qemu-devel] [PULL 00/11] target-mips queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 00/11] target-mips queue |
Date: |
Tue, 12 Jul 2016 13:03:22 +0100 |
On 12 July 2016 at 12:14, Leon Alrae <address@hidden> wrote:
> Hi,
>
> This pull request adds MIPS CPS features needed to boot MIPSr6 SMP Linux on
> multiple VPs, renames MIPS64R6-generic to I6400 and adds 10-bit ASID support.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
>
> The following changes since commit e2c8f9e44e07d8210049abaa6042ec3c956f1dd4:
>
> Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into
> staging (2016-07-04 10:49:17 +0100)
>
> are available in the git repository at:
>
> git://github.com/lalrae/qemu.git tags/mips-20160712
>
> for you to fetch changes up to cdc46fab07a122dfcc8a1054510a68d936ae3440:
>
> target-mips: enable 10-bit ASIDs in I6400 CPU (2016-07-12 09:10:21 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-07-12
>
> Changes:
> * support 10-bit ASIDs
> * MIPS64R6-generic renamed to I6400
> * initial GIC support
> * implement RESET_BASE register in CM GCR
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
- [Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS, (continued)
- [Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 02/11] hw/mips: implement Global Interrupt Controller, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 07/11] target-mips: replace MIPS64R6-generic with the real I6400 CPU model, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 06/11] hw/mips_cmgcr: implement RESET_BASE register in CM GCR, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 11/11] target-mips: enable 10-bit ASIDs in I6400 CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 08/11] target-mips: add ASID mask field and replace magic values, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit, Leon Alrae, 2016/07/12
- Re: [Qemu-devel] [PULL 00/11] target-mips queue,
Peter Maydell <=