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[Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer |
Date: |
Tue, 12 Jul 2016 12:14:47 +0100 |
From: Yongbok Kim <address@hidden>
The interval timer is similar to the CP0 Count/Compare timer within
each processor. The difference is the GIC_SH_COUNTER register is global
to the system so that all processors have the same time reference.
To ease implementation, all VPs are having its own QEMU timer but sharing
global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and
GIC_SH_COUNTER.
MIPS GIC Interval Timer does support upto 64 bits of Count register but
in this implementation it is limited to 32 bits only.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
hw/timer/Makefile.objs | 1 +
hw/timer/mips_gictimer.c | 142 +++++++++++++++++++++++++++++++++++++++
include/hw/timer/mips_gictimer.h | 46 +++++++++++++
3 files changed, 189 insertions(+)
create mode 100644 hw/timer/mips_gictimer.c
create mode 100644 include/hw/timer/mips_gictimer.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 003c14f..7ba8c23 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP) += omap_synctimer.o
obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
obj-$(CONFIG_SH4) += sh_timer.o
obj-$(CONFIG_DIGIC) += digic-timer.o
+obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
diff --git a/hw/timer/mips_gictimer.c b/hw/timer/mips_gictimer.c
new file mode 100644
index 0000000..3698889
--- /dev/null
+++ b/hw/timer/mips_gictimer.c
@@ -0,0 +1,142 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/timer/mips_gictimer.h"
+
+#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
+
+static void gic_vptimer_update(MIPSGICTimerState *gictimer,
+ uint32_t vp_index, uint64_t now)
+{
+ uint64_t next;
+ uint32_t wait;
+
+ wait = gictimer->vptimers[vp_index].comparelo - gictimer->sh_counterlo -
+ (uint32_t)(now / TIMER_PERIOD);
+ next = now + (uint64_t)wait * TIMER_PERIOD;
+
+ timer_mod(gictimer->vptimers[vp_index].qtimer, next);
+}
+
+static void gic_vptimer_expire(MIPSGICTimerState *gictimer, uint32_t vp_index,
+ uint64_t now)
+{
+ if (gictimer->countstop) {
+ /* timer stopped */
+ return;
+ }
+ gictimer->cb(gictimer->opaque, vp_index);
+ gic_vptimer_update(gictimer, vp_index, now);
+}
+
+static void gic_vptimer_cb(void *opaque)
+{
+ MIPSGICTimerVPState *vptimer = opaque;
+ MIPSGICTimerState *gictimer = vptimer->gictimer;
+ gic_vptimer_expire(gictimer, vptimer->vp_index,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
+}
+
+uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gictimer)
+{
+ int i;
+ if (gictimer->countstop) {
+ return gictimer->sh_counterlo;
+ } else {
+ uint64_t now;
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ for (i = 0; i < gictimer->num_vps; i++) {
+ if (timer_pending(gictimer->vptimers[i].qtimer)
+ && timer_expired(gictimer->vptimers[i].qtimer, now)) {
+ /* The timer has already expired. */
+ gic_vptimer_expire(gictimer, i, now);
+ }
+ }
+ return gictimer->sh_counterlo + (uint32_t)(now / TIMER_PERIOD);
+ }
+}
+
+void mips_gictimer_store_sh_count(MIPSGICTimerState *gictimer, uint64_t count)
+{
+ int i;
+ uint64_t now;
+
+ if (gictimer->countstop || !gictimer->vptimers[0].qtimer) {
+ gictimer->sh_counterlo = count;
+ } else {
+ /* Store new count register */
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ gictimer->sh_counterlo = count - (uint32_t)(now / TIMER_PERIOD);
+ /* Update timer timer */
+ for (i = 0; i < gictimer->num_vps; i++) {
+ gic_vptimer_update(gictimer, i, now);
+ }
+ }
+}
+
+uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
+ uint32_t vp_index)
+{
+ return gictimer->vptimers[vp_index].comparelo;
+}
+
+void mips_gictimer_store_vp_compare(MIPSGICTimerState *gictimer,
+ uint32_t vp_index, uint64_t compare)
+{
+ gictimer->vptimers[vp_index].comparelo = (uint32_t) compare;
+ gic_vptimer_update(gictimer, vp_index,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
+}
+
+uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gictimer)
+{
+ return gictimer->countstop;
+}
+
+void mips_gictimer_start_count(MIPSGICTimerState *gictimer)
+{
+ gictimer->countstop = 0;
+ mips_gictimer_store_sh_count(gictimer, gictimer->sh_counterlo);
+}
+
+void mips_gictimer_stop_count(MIPSGICTimerState *gictimer)
+{
+ int i;
+
+ gictimer->countstop = 1;
+ /* Store the current value */
+ gictimer->sh_counterlo +=
+ (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
+ for (i = 0; i < gictimer->num_vps; i++) {
+ timer_del(gictimer->vptimers[i].qtimer);
+ }
+}
+
+MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
+ MIPSGICTimerCB *cb)
+{
+ int i;
+ MIPSGICTimerState *gictimer = g_new(MIPSGICTimerState, 1);
+ gictimer->vptimers = g_new(MIPSGICTimerVPState, nvps);
+ gictimer->countstop = 1;
+ gictimer->num_vps = nvps;
+ gictimer->opaque = opaque;
+ gictimer->cb = cb;
+ for (i = 0; i < nvps; i++) {
+ gictimer->vptimers[i].gictimer = gictimer;
+ gictimer->vptimers[i].vp_index = i;
+ gictimer->vptimers[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ &gic_vptimer_cb,
+ &gictimer->vptimers[i]);
+ }
+ return gictimer;
+}
diff --git a/include/hw/timer/mips_gictimer.h b/include/hw/timer/mips_gictimer.h
new file mode 100644
index 0000000..e3ca45c
--- /dev/null
+++ b/include/hw/timer/mips_gictimer.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ */
+
+#ifndef _MIPS_GICTIMER_H_
+#define _MIPS_GICTIMER_H_
+
+typedef struct MIPSGICTimerVPState MIPSGICTimerVPState;
+typedef struct MIPSGICTimerState MIPSGICTimerState;
+
+typedef void MIPSGICTimerCB(void *opaque, uint32_t vp_index);
+
+struct MIPSGICTimerVPState {
+ QEMUTimer *qtimer;
+ uint32_t vp_index;
+ uint32_t comparelo;
+ MIPSGICTimerState *gictimer;
+};
+
+struct MIPSGICTimerState {
+ void *opaque;
+ uint8_t countstop;
+ uint32_t sh_counterlo;
+ int32_t num_vps;
+ MIPSGICTimerVPState *vptimers;
+ MIPSGICTimerCB *cb;
+};
+
+uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
+void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
+uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer,
+ uint32_t vp_index);
+void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
+ uint64_t compare);
+uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
+void mips_gictimer_start_count(MIPSGICTimerState *gic);
+void mips_gictimer_stop_count(MIPSGICTimerState *gic);
+MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
+ MIPSGICTimerCB *cb);
+
+#endif /* _MIPS_GICTIMER_H_ */
--
2.7.4
- [Qemu-devel] [PULL 00/11] target-mips queue, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer,
Leon Alrae <=
- [Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 02/11] hw/mips: implement Global Interrupt Controller, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 07/11] target-mips: replace MIPS64R6-generic with the real I6400 CPU model, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 06/11] hw/mips_cmgcr: implement RESET_BASE register in CM GCR, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 11/11] target-mips: enable 10-bit ASIDs in I6400 CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 08/11] target-mips: add ASID mask field and replace magic values, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit, Leon Alrae, 2016/07/12